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Change subject: mb/amd/birman/devicetree_phoenix: update USB PHY settings
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75823/comment/13b279cc_eb51356d :
PS1, Line 16: TEST=None
> would be good to test this on the board
Tested on birman - USB functioned as expected
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Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69870?usp=email )
(
5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: intel/cmn/smm: Introduce PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B
......................................................................
intel/cmn/smm: Introduce PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B
Certain chipsets/SoCs like Apollo Lake use GEN_PMCON_B for periodic SMI
rate selection unlike other chipsets which use GEN_PMCON_A. Introduce new Kconfig option PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B to
indicate the register difference.
Based on Apollo Lake datasheet Vol. 3 Revision 005:
https://cdrdv2.intel.com/v1/dl/getContent/334819
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I11241836ecc9066d323977b030686567c87ed256
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69870
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Sean Rhodes <sean(a)starlabs.systems>
Reviewed-by: Krystian Hebel <krystian.hebel(a)3mdeb.com>
---
M src/soc/intel/common/block/smm/Kconfig
1 file changed, 9 insertions(+), 0 deletions(-)
Approvals:
Krystian Hebel: Looks good to me, approved
build bot (Jenkins): Verified
Sean Rhodes: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/common/block/smm/Kconfig b/src/soc/intel/common/block/smm/Kconfig
index 2d960d6..4944ade 100644
--- a/src/soc/intel/common/block/smm/Kconfig
+++ b/src/soc/intel/common/block/smm/Kconfig
@@ -44,3 +44,12 @@
help
HECI disable using SMM. Select this option to make HECI disable
using SMM mode, independent of dedicated UPD to perform HECI disable.
+
+config PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B
+ bool
+ depends on SOC_INTEL_COMMON_BLOCK_SMM
+ default n
+ help
+ Intel Core processors select the periodic SMI rate via GEN_PMCON_A.
+ On Intel Atom processors the register is different and they use
+ GEN_PMCON_B/GEN_PMCON2 with different address.
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Change subject: intel/cmn/smm: Introduce PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B
......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69870/comment/422d496a_bef86977 :
PS5, Line 10: rate seletion unlike other chipsets which use GEN_PMCON_A. Introduce new
> nit: selection
Done
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to look at the new patch set (#7).
Change subject: intel/cmn/smm: Introduce PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B
......................................................................
intel/cmn/smm: Introduce PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B
Certain chipsets/SoCs like Apollo Lake use GEN_PMCON_B for periodic SMI
rate selection unlike other chipsets which use GEN_PMCON_A. Introduce new Kconfig option PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B to
indicate the register difference.
Based on Apollo Lake datasheet Vol. 3 Revision 005:
https://cdrdv2.intel.com/v1/dl/getContent/334819
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I11241836ecc9066d323977b030686567c87ed256
---
M src/soc/intel/common/block/smm/Kconfig
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/69870/7
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Change subject: intel/cmn/smm: Introduce PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B
......................................................................
intel/cmn/smm: Introduce PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B
Certain chipsets/SoCs like Apollo Lake use GEN_PMCON_B for periodic SMI
rate selection unlike other chipsets which use GEN_PMCON_A. Introduce new
Kconfig option PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B to indicate
the register difference.
Based on Apollo Lake datasheet Vol. 3 Revision 005:
https://cdrdv2.intel.com/v1/dl/getContent/334819
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I11241836ecc9066d323977b030686567c87ed256
---
M src/soc/intel/common/block/smm/Kconfig
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/69870/6
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Change subject: soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash
......................................................................
Patch Set 9:
(1 comment)
Patchset:
PS8:
> One typo caught by Jenkins left.
Fixed
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Code-Review+1 by Krystian Hebel
Change subject: soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash
......................................................................
soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash
The patch adds a possibility to cache the PCIe 5.0 HSPHY firmware in
the SPI flash. New flashmap region is created for that purpose. The
goal of caching is to reduce the dependency on CSME and the HECI IP
LOAD command which may fail when the CSME is disabled, e.g. soft
disabled by HECI command or HAP disabled. This change allows to
keep PCIe 5.0 root ports functioning even if CSME/HECI is not
functional.
TEST=Boot Ubuntu 22.04 on MSI PRO Z690-A and notice PCIe 5.0 port
is functional after loading the HSPHY from cache.
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I5a37f5b06706ff30d92f60f1bf5dc900edbde96f
---
M Makefile.inc
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/Makefile.inc
M src/soc/intel/alderlake/hsphy.c
M util/cbfstool/default-x86.fmd
5 files changed, 309 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/68987/9
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Change subject: ChromeOS: Move CRHW device object
......................................................................
Patch Set 12:
(1 comment)
Patchset:
PS12:
> > I'm not an ACPI expert - subratabanik@ do you have some idea who can review this? […]
Note the previous comment in patchset #11. TimW considered the coreboot change valid (to fix ACPI spec violation in firmware) but meeting the spec would have to reflected in OS kernel.
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Change subject: ChromeOS: Move CRHW device object
......................................................................
Patch Set 12:
(1 comment)
Patchset:
PS12:
> I'm not an ACPI expert - subratabanik@ do you have some idea who can review this?
I will take a look
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