coreboot-gerrit June 2023

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[S] Change in coreboot[master]: soc/intel/apollolake: Switch to snake case for ModPhyIfValue
by Mario Scheithauer (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Sean Rhodes. Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75855?usp=email ) Change subject: soc/intel/apollolake: Switch to snake case for ModPhyIfValue ...................................................................... soc/intel/apollolake: Switch to snake case for ModPhyIfValue For a unification of the naming convension, change from pascal case to snake case style for parameter 'ModPhyIfValue'. Change-Id: I4cdf68e65cea4ab316af969cd6a8d096b456518d Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/google/octopus/variants/baseboard/devicetree.cb M src/mainboard/starlabs/lite/variants/glk/devicetree.cb M src/mainboard/starlabs/lite/variants/glkr/devicetree.cb M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 5 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/75855/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index fdfcd61..c6bfe54 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -290,5 +290,5 @@ # FSP UPD to modify the Integrated Filter (IF) value # Set it to default value: 0x12 - register "ModPhyIfValue" = "0x12" + register "mod_phy_if_value" = "0x12" end diff --git a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb index abfbc0a..2f58a7b 100644 --- a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb @@ -26,7 +26,7 @@ register "pnp_settings" = "PNP_PERF_POWER" - register "ModPhyIfValue" = "0x12" + register "mod_phy_if_value" = "0x12" register "prt0_gpio" = "GPIO_PRT0_UDEF" diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb index 3102b1f..fe32143c5d 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb @@ -26,7 +26,7 @@ register "pnp_settings" = "PNP_PERF_POWER" - register "ModPhyIfValue" = "0x12" + register "mod_phy_if_value" = "0x12" register "prt0_gpio" = "GPIO_PRT0_UDEF" diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index e3bfa1e..a29ba3b 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -612,7 +612,7 @@ /* * Options to change USB3 ModPhy setting for Integrated Filter value. */ - silconfig->ModPhyIfValue = cfg->ModPhyIfValue; + silconfig->ModPhyIfValue = cfg->mod_phy_if_value; /* * Options to bump USB3 LDO voltage with 40mv. diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index c1bc020..26e4478 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -190,7 +190,7 @@ * value. Default is 0 to not changing default IF value (0x12). Set * value with the range from 0x01 to 0xff to change IF value. */ - uint8_t ModPhyIfValue; + uint8_t mod_phy_if_value; /* Options to bump USB3 LDO voltage. Default is FALSE to not increasing * LDO voltage. Set TRUE to increase LDO voltage with 40mV. -- To view, visit https://review.coreboot.org/c/coreboot/+/75855?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cdf68e65cea4ab316af969cd6a8d096b456518d Gerrit-Change-Number: 75855 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/apollolake: Switch to snake case for DisableComplianceMode
by Mario Scheithauer (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Sean Rhodes. Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75854?usp=email ) Change subject: soc/intel/apollolake: Switch to snake case for DisableComplianceMode ...................................................................... soc/intel/apollolake: Switch to snake case for DisableComplianceMode For a unification of the naming convension, change from pascal case to snake case style for parameter 'DisableComplianceMode'. Change-Id: I9d5605134a753f161a66857c7f78844ae7490cd6 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/google/octopus/variants/bloog/overridetree.cb M src/mainboard/google/octopus/variants/bobba/overridetree.cb M src/mainboard/google/octopus/variants/casta/overridetree.cb M src/mainboard/google/octopus/variants/dood/overridetree.cb M src/mainboard/google/octopus/variants/fleex/overridetree.cb M src/mainboard/google/octopus/variants/foob/overridetree.cb M src/mainboard/google/octopus/variants/garg/overridetree.cb M src/mainboard/google/octopus/variants/lick/overridetree.cb M src/mainboard/google/octopus/variants/meep/overridetree.cb M src/mainboard/google/octopus/variants/phaser/overridetree.cb M src/mainboard/starlabs/lite/variants/glk/devicetree.cb M src/mainboard/starlabs/lite/variants/glkr/devicetree.cb M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 14 files changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/75854/1 diff --git a/src/mainboard/google/octopus/variants/bloog/overridetree.cb b/src/mainboard/google/octopus/variants/bloog/overridetree.cb index 83880ec..b4388c1 100644 --- a/src/mainboard/google/octopus/variants/bloog/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bloog/overridetree.cb @@ -168,5 +168,5 @@ end # Disable compliance mode - register "DisableComplianceMode" = "1" + register "disable_compliance_mode" = "1" end diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb index 8a48d22..31c1463 100644 --- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb @@ -227,6 +227,6 @@ end # Disable compliance mode - register "DisableComplianceMode" = "1" + register "disable_compliance_mode" = "1" register "disable_xhci_lfps_pm" = "0" end diff --git a/src/mainboard/google/octopus/variants/casta/overridetree.cb b/src/mainboard/google/octopus/variants/casta/overridetree.cb index dce4d00..c7540c8 100644 --- a/src/mainboard/google/octopus/variants/casta/overridetree.cb +++ b/src/mainboard/google/octopus/variants/casta/overridetree.cb @@ -150,5 +150,5 @@ end # Disable compliance mode - register "DisableComplianceMode" = "1" + register "disable_compliance_mode" = "1" end diff --git a/src/mainboard/google/octopus/variants/dood/overridetree.cb b/src/mainboard/google/octopus/variants/dood/overridetree.cb index de923c4..9b4126d 100644 --- a/src/mainboard/google/octopus/variants/dood/overridetree.cb +++ b/src/mainboard/google/octopus/variants/dood/overridetree.cb @@ -162,6 +162,6 @@ end # Disable compliance mode - register "DisableComplianceMode" = "1" + register "disable_compliance_mode" = "1" register "disable_xhci_lfps_pm" = "0" end diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb index 9a4cdee..b8444e5 100644 --- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb +++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb @@ -85,7 +85,7 @@ }" # Disable compliance mode - register "DisableComplianceMode" = "1" + register "disable_compliance_mode" = "1" register "disable_xhci_lfps_pm" = "0" device domain 0 on diff --git a/src/mainboard/google/octopus/variants/foob/overridetree.cb b/src/mainboard/google/octopus/variants/foob/overridetree.cb index c47b0de..274aead 100644 --- a/src/mainboard/google/octopus/variants/foob/overridetree.cb +++ b/src/mainboard/google/octopus/variants/foob/overridetree.cb @@ -163,5 +163,5 @@ end # Disable xHCI compliance mode - register "DisableComplianceMode" = "1" + register "disable_compliance_mode" = "1" end diff --git a/src/mainboard/google/octopus/variants/garg/overridetree.cb b/src/mainboard/google/octopus/variants/garg/overridetree.cb index 86b4342..459e5b3 100644 --- a/src/mainboard/google/octopus/variants/garg/overridetree.cb +++ b/src/mainboard/google/octopus/variants/garg/overridetree.cb @@ -204,6 +204,6 @@ end # Disable compliance mode - register "DisableComplianceMode" = "1" + register "disable_compliance_mode" = "1" register "disable_xhci_lfps_pm" = "0" end diff --git a/src/mainboard/google/octopus/variants/lick/overridetree.cb b/src/mainboard/google/octopus/variants/lick/overridetree.cb index b74417b..551a2ba 100644 --- a/src/mainboard/google/octopus/variants/lick/overridetree.cb +++ b/src/mainboard/google/octopus/variants/lick/overridetree.cb @@ -116,5 +116,5 @@ # Disable compliance mode - register "DisableComplianceMode" = "1" + register "disable_compliance_mode" = "1" end diff --git a/src/mainboard/google/octopus/variants/meep/overridetree.cb b/src/mainboard/google/octopus/variants/meep/overridetree.cb index 6623fa0..727b468 100644 --- a/src/mainboard/google/octopus/variants/meep/overridetree.cb +++ b/src/mainboard/google/octopus/variants/meep/overridetree.cb @@ -248,5 +248,5 @@ end # Disable compliance mode - register "DisableComplianceMode" = "1" + register "disable_compliance_mode" = "1" end diff --git a/src/mainboard/google/octopus/variants/phaser/overridetree.cb b/src/mainboard/google/octopus/variants/phaser/overridetree.cb index 748481d..472676f 100644 --- a/src/mainboard/google/octopus/variants/phaser/overridetree.cb +++ b/src/mainboard/google/octopus/variants/phaser/overridetree.cb @@ -202,5 +202,5 @@ end # Disable xHCI compliance mode - register "DisableComplianceMode" = "1" + register "disable_compliance_mode" = "1" end diff --git a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb index fb9070f..abfbc0a 100644 --- a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb @@ -31,7 +31,7 @@ register "prt0_gpio" = "GPIO_PRT0_UDEF" register "usb_config_override" = "1" - register "DisableComplianceMode" = "1" + register "disable_compliance_mode" = "1" register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb index b4e627c..3102b1f 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb @@ -31,7 +31,7 @@ register "prt0_gpio" = "GPIO_PRT0_UDEF" register "usb_config_override" = "1" - register "DisableComplianceMode" = "1" + register "disable_compliance_mode" = "1" register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 57aa085..e3bfa1e 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -607,7 +607,7 @@ /* * Options to disable XHCI Link Compliance Mode. */ - silconfig->DisableComplianceMode = cfg->DisableComplianceMode; + silconfig->DisableComplianceMode = cfg->disable_compliance_mode; /* * Options to change USB3 ModPhy setting for Integrated Filter value. diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 88ec1ff..c1bc020 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -184,7 +184,7 @@ * disable Compliance Mode. Set TRUE to disable Compliance Mode. * 0:FALSE(Default), 1:True. */ - uint8_t DisableComplianceMode; + uint8_t disable_compliance_mode; /* Options to change USB3 ModPhy setting for the Integrated Filter (IF) * value. Default is 0 to not changing default IF value (0x12). Set -- To view, visit https://review.coreboot.org/c/coreboot/+/75854?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d5605134a753f161a66857c7f78844ae7490cd6 Gerrit-Change-Number: 75854 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/apollolake: Switch to snake case for PmicPmcIpcCtrl
by Mario Scheithauer (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Sean Rhodes. Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75853?usp=email ) Change subject: soc/intel/apollolake: Switch to snake case for PmicPmcIpcCtrl ...................................................................... soc/intel/apollolake: Switch to snake case for PmicPmcIpcCtrl For a unification of the naming convension, change from pascal case to snake case style for parameter 'PmicPmcIpcCtrl'. Change-Id: I3632d1e83108221d3487b4f175133ad347238bc5 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/google/octopus/variants/baseboard/devicetree.cb M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 3 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/75853/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index c001dbe..fdfcd61 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -275,18 +275,18 @@ # RegOrValue (15:8): 0x2 and RegAndValue (7:0) 0xF8. # The register is defined as: D[7:3] RSVD, D[2:0] PWROKDELAY. # uint8 RegOrValue, RegAndValue, PmicReadReg - # RegOrValue = (UINT8)((PmicPmcIpcCtrl >> 8) & 0xff); - # RegAndValue = (UINT8)(PmicPmcIpcCtrl & 0xff); + # RegOrValue = (UINT8)((pmic_pmc_ipc_ctrl >> 8) & 0xff); + # RegAndValue = (UINT8)(pmic_pmc_ipc_ctrl & 0xff); # PmicReadReg &= RegAndValue; # PmicReadReg |= RegOrValue; # PmicReadReg value will be programmed into PMIC D[2:0] PWROKDELAY field # and D[7:3] RSVD will not be impacted. - # Configure PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay + # Configure pmic_pmc_ipc_ctrl for PMC to program PMIC PCH_PWROK delay # from 100ms to 10ms. # PWROKDELAY[2:0]: 000=2.5ms, 001=5.0ms, 010=10ms, 011=15ms, 100=20ms, # 101=50ms, 110=75ms, 111=100ms (default) - register "PmicPmcIpcCtrl" = "0x5e4302f8" + register "pmic_pmc_ipc_ctrl" = "0x5e4302f8" # FSP UPD to modify the Integrated Filter (IF) value # Set it to default value: 0x12 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 76a6cc4..57aa085 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -602,7 +602,7 @@ * improve boot performance, configure PmicPmcIpcCtrl for PMC to program * PMIC PCH_PWROK delay. */ - silconfig->PmicPmcIpcCtrl = cfg->PmicPmcIpcCtrl; + silconfig->PmicPmcIpcCtrl = cfg->pmic_pmc_ipc_ctrl; /* * Options to disable XHCI Link Compliance Mode. diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index fa22415..88ec1ff 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -178,7 +178,7 @@ * Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address * (31:24) + Register_Offset (23:16) + OR Value (15:8) + AND Value (7:0) */ - uint32_t PmicPmcIpcCtrl; + uint32_t pmic_pmc_ipc_ctrl; /* Options to disable XHCI Link Compliance Mode. Default is FALSE to not * disable Compliance Mode. Set TRUE to disable Compliance Mode. -- To view, visit https://review.coreboot.org/c/coreboot/+/75853?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3632d1e83108221d3487b4f175133ad347238bc5 Gerrit-Change-Number: 75853 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: soc/intel/apollolake: Switch to snake case for SataPortsHotPlug
by Mario Scheithauer (Code Review) 15 Jun '23

15 Jun '23

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75852?usp=email ) Change subject: soc/intel/apollolake: Switch to snake case for SataPortsHotPlug ...................................................................... soc/intel/apollolake: Switch to snake case for SataPortsHotPlug For a unification of the naming convension, change from pascal case to snake case style for parameter 'SataPortsHotPlug'. Change-Id: I8fc8b30ac2c182ffaf2dee37e0116e27071b6a2c Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/75852/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 9ec52b1..76a6cc4 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -689,7 +689,7 @@ if (cfg->emmc_host_max_speed != 0) silconfig->eMMCHostMaxSpeed = cfg->emmc_host_max_speed; - memcpy(silconfig->SataPortsHotPlug, cfg->SataPortsHotPlug, + memcpy(silconfig->SataPortsHotPlug, cfg->sata_ports_hot_plug, sizeof(silconfig->SataPortsHotPlug)); silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index b956252..fa22415 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -104,7 +104,7 @@ uint8_t emmc_host_max_speed; /* Sata Ports Hot Plug */ - uint8_t SataPortsHotPlug[2]; + uint8_t sata_ports_hot_plug[2]; /* Sata Ports Enable */ uint8_t sata_ports_enable[2]; -- To view, visit https://review.coreboot.org/c/coreboot/+/75852?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fc8b30ac2c182ffaf2dee37e0116e27071b6a2c Gerrit-Change-Number: 75852 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: [WIP] mb/lippert/frontrunner-af: Use common cimx/sb800 fch.asl
by Kyösti Mälkki (Code Review) 15 Jun '23

15 Jun '23

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/59181?usp=email ) Change subject: [WIP] mb/lippert/frontrunner-af: Use common cimx/sb800 fch.asl ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/59181?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0516d50b079c8f60312329eef36ca17ea3c94468 Gerrit-Change-Number: 59181 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[master]: soc/intel/baytrail: Drop runtime ACPI mode change via SMI
by Kyösti Mälkki (Code Review) 15 Jun '23

15 Jun '23

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/49492?usp=email ) Change subject: soc/intel/baytrail: Drop runtime ACPI mode change via SMI ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/49492?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76736fa72af30003d86dfc2551b673037c1dd522 Gerrit-Change-Number: 49492 Gerrit-PatchSet: 12 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: soc/amd/*/root_complex: reserve IOMMU MMIO area
by Felix Held (Code Review) 15 Jun '23

15 Jun '23

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75611?usp=email ) Change subject: soc/amd/*/root_complex: reserve IOMMU MMIO area ...................................................................... Patch Set 5: (2 comments) Patchset: PS4: > btw, quick look read_resources could be common code. ideally the common code for that should be split into the x86 architecture specific, silicon specific and fsp integration specific parts. still need to look into that, but it's not a too high priority for me at the moment PS4: > I found the following in docs. I guess reserving the full 4G is a good idea. […] yes, that's the part of the doc i looked at. the default address for the rom3 full spi flash mapping defaults to the same address; not sure why that is the case, but still seems to work. instead of those 3 regions that cover most of the 4GB, i just reserved the full 4GB -- To view, visit https://review.coreboot.org/c/coreboot/+/75611?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a8150873cb019ca1d903ed269e18d6f9fabb871 Gerrit-Change-Number: 75611 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Thu, 15 Jun 2023 12:19:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: ChromeOS: Move CRHW device object
by Hung-Te Lin (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Kyösti Mälkki, Raul Rangel, Subrata Banik. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58421?usp=email ) Change subject: ChromeOS: Move CRHW device object ...................................................................... Patch Set 12: (1 comment) Patchset: PS12: I'm not an ACPI expert - subratabanik@ do you have some idea who can review this? -- To view, visit https://review.coreboot.org/c/coreboot/+/58421?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I449d0206fbaee94cea99f745cf297ad293e8306c Gerrit-Change-Number: 58421 Gerrit-PatchSet: 12 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 15 Jun 2023 12:18:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: CBMEM: Drop cbmem_initialize_empty()
by Kyösti Mälkki (Code Review) 15 Jun '23

15 Jun '23

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/50987?usp=email ) Change subject: CBMEM: Drop cbmem_initialize_empty() ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/50987?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf45f4d3cddfd8f85dee99d5bd906f15c308d847 Gerrit-Change-Number: 50987 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[master]: [WIP] CBMEM: Always reset on ACPI S3 resume failures
by Kyösti Mälkki (Code Review) 15 Jun '23

15 Jun '23

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/50976?usp=email ) Change subject: [WIP] CBMEM: Always reset on ACPI S3 resume failures ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/50976?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3301a11e494684d1991c919293eb4f2dc335500f Gerrit-Change-Number: 50976 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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