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Change subject: soc/intel/apollolake: Fix FSP SATA speed limit configuraion
......................................................................
Patch Set 7:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75820/comment/41ade795_06f27ab3 :
PS5, Line 21: SATA configuration via dmesg
> Maybe more detailed, usually there is something like: […]
Done
File src/soc/intel/apollolake/ahci.c:
https://review.coreboot.org/c/coreboot/+/75820/comment/21b685c9_7307349b :
PS5, Line 12:
> 'is set, ' or 'is given, ', ... […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/75820/comment/70cb5fc0_d871d32d :
PS5, Line 21: u
> I think, the enum type defaults to int in C, therefore `%d`.
Done
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Hello Felix Singer, Jan Samek, Sean Rhodes, Werner Zeh, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/apollolake: Fix FSP SATA speed limit configuraion
......................................................................
soc/intel/apollolake: Fix FSP SATA speed limit configuraion
With commit f165bbdcf043 ("soc/intel/apollolake: Make SATA speed limit
configurable") came the expansion to adjust the SATA speed.
Unfortunately, APL FSP-S sets only the default value, so Gen 3, and
ignores the passing parameter value. Since the corresponding register
entry can only be changed once, the setting must be made on coreboot
side before FSP-S is called. This patch fixes the SATA speed
configuration for Apollo Lake CPUs.
Link to Intel Pentium and Celeron N- and J- series datasheet volume 2:
https://web.archive.org/web/20230614130311/https://www.intel.com/content/ww…
BUG=none
TEST=Boot into Linux and check SATA configuration via dmesg
ahci 0000:00:12.0: AHCI 0001.0301 32 slots 1 ports 3 Gbps 0x1 impl SATA
mode
ata1: SATA max UDMA/133 abar m2048@0x9872a000 port 0x9872a100 irq 126
ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
Change-Id: I6f55f40941fa618e7de13a5cefe9e17ae34c5c99
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/soc/intel/apollolake/Makefile.inc
A src/soc/intel/apollolake/ahci.c
M src/soc/intel/apollolake/chip.c
A src/soc/intel/apollolake/include/soc/ahci.h
4 files changed, 48 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/75820/7
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Change subject: soc/intel/apollolake: Fix FSP SATA speed limit configuraion
......................................................................
soc/intel/apollolake: Fix FSP SATA speed limit configuraion
With commit f165bbdcf043 ("soc/intel/apollolake: Make SATA speed limit
configurable") came the expansion to adjust the SATA speed.
Unfortunately, APL FSP-S sets only the default value, so Gen 3, and
ignores the passing parameter value. Since the corresponding register
entry can only be changed once, the setting must be made on coreboot
side before FSP-S is called. This patch fixes the SATA speed
configuration for Apollo Lake CPUs.
Link to Intel Pentium and Celeron N- and J- series datasheet volume 2:
https://web.archive.org/web/20230614130311/https://www.intel.com/content/ww…
BUG=none
TEST=Boot into Linux and check SATA configuration via dmesg
Change-Id: I6f55f40941fa618e7de13a5cefe9e17ae34c5c99
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/soc/intel/apollolake/Makefile.inc
A src/soc/intel/apollolake/ahci.c
M src/soc/intel/apollolake/chip.c
A src/soc/intel/apollolake/include/soc/ahci.h
4 files changed, 48 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/75820/6
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Change subject: soc/intel/apollolake: Fix FSP SATA speed limit configuraion
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75820/comment/d85e4770_d59769c5 :
PS5, Line 21: SATA configuration via dmesg
Maybe more detailed, usually there is something like:
```
ata1: SATA link up 6.0 Gbps
```
so maybe "that the reported speed of the link matches with the setting"?
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Change subject: soc/intel/apollolake: Fix FSP SATA speed limit configuraion
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/apollolake/ahci.c:
https://review.coreboot.org/c/coreboot/+/75820/comment/02cdd01e_b5484361 :
PS5, Line 21: u
I think, the enum type defaults to int in C, therefore `%d`.
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Change subject: soc/intel/apollolake: Fix FSP SATA speed limit configuraion
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/apollolake/ahci.c:
https://review.coreboot.org/c/coreboot/+/75820/comment/bd6ed9a9_2fc809c1 :
PS5, Line 12:
'is set, ' or 'is given, ', ...
...Or is this comment needed at all? It says exactly the same thing as the code.
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Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75850?usp=email )
Change subject: docs/flashmap: Document available flashmap flags
......................................................................
docs/flashmap: Document available flashmap flags
Add the missing flag 'PRESERVE' that was introduced from
https://review.coreboot.org/c/coreboot/+/31766.
Change-Id: Iada0fcb0ada1573acfbb51b5f6bf723fb8b68ba8
Signed-off-by: Hung-Te Lin <hungte(a)chromium.org>
---
M Documentation/lib/flashmap.md
1 file changed, 4 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/75850/1
diff --git a/Documentation/lib/flashmap.md b/Documentation/lib/flashmap.md
index f0816cf..8b8acc8 100644
--- a/Documentation/lib/flashmap.md
+++ b/Documentation/lib/flashmap.md
@@ -111,9 +111,10 @@
* Just because something is noted as optional doesn't mean it is in every case:
the answer might actually depend on which other information is---or
isn't---provided.
-* The "flag" specifies the attribute or type for given section. The most
- important supported flag is "CBFS", which indicates the section will contain
- a CBFS structure.
+* The "flag" specifies the attribute or type for given section. That includes:
+ * `CBFS`: indicates the section will contain a CBFS structure.
+ * `PRESERVE`: the contents must be preserved during firmware update or
+ recovery.
* In particular, it is only legal to place a (CBFS) flag on a leaf section; that
is, choosing to add child sections excludes the possibility of putting a CBFS
in their parent. Such flags are only used to decide where CBFS empty file
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Change subject: mb/google/rex: Set AUX orientation at SoC to follow cable for anx7452
......................................................................
Patch Set 2: Code-Review+2
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