coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: lib/fw_config: Make fw_config_is_provisioned() always available
by Jakub Czapiga (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Eric Lai, Julius Werner, Martin L Roth. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75835?usp=email ) Change subject: lib/fw_config: Make fw_config_is_provisioned() always available ...................................................................... Patch Set 2: (1 comment) File src/lib/fw_config.c: https://review.coreboot.org/c/coreboot/+/75835/comment/f691187d_d9631ce8 : PS1, Line 100: return fw_config_get() != UNDEFINED_FW_CONFIG; > FW config may not provision in SMT. We need this check I think. […] OK, so I moved `fw_config_is_provisioned()` implementation to the header file. `fw_config_get()` has weak implementation in the `src/lib/coreboot_table.c`, so it will always be available. -- To view, visit https://review.coreboot.org/c/coreboot/+/75835?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ea21b19339cd93ba78dbe25213cbfb40e012937 Gerrit-Change-Number: 75835 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 15 Jun 2023 08:53:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/apollolake: Fix FSP SATA speed limit configuraion
by Eric Lai (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Felix Singer, Jan Samek, Mario Scheithauer, Sean Rhodes, Werner Zeh. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75820?usp=email ) Change subject: soc/intel/apollolake: Fix FSP SATA speed limit configuraion ...................................................................... Patch Set 5: (2 comments) Patchset: PS5: why not ask FSP to fix File src/soc/intel/apollolake/include/soc/ahci.h: https://review.coreboot.org/c/coreboot/+/75820/comment/b164a9bc_528f31c0 : PS5, Line 12: extra space -- To view, visit https://review.coreboot.org/c/coreboot/+/75820?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f55f40941fa618e7de13a5cefe9e17ae34c5c99 Gerrit-Change-Number: 75820 Gerrit-PatchSet: 5 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Comment-Date: Thu, 15 Jun 2023 08:50:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: {driver, mb, soc}: Store fw versions in CMOS memory for cold boot
by Subrata Banik (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Dinesh Gehlot, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75755?usp=email ) Change subject: {driver, mb, soc}: Store fw versions in CMOS memory for cold boot ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/75755/comment/f626a94e_1e915582 : PS7, Line 1176: * Helper function that stores current CSE firmware version to CBMEM, except : * during recovery mode. u can do it later during clean up cl -- To view, visit https://review.coreboot.org/c/coreboot/+/75755?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc5a027aa2bb7217e5032f56fece0846783557a5 Gerrit-Change-Number: 75755 Gerrit-PatchSet: 7 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 15 Jun 2023 08:37:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [fixup] coccinelle issues
by Kyösti Mälkki (Code Review) 15 Jun '23

15 Jun '23

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/65009?usp=email ) Change subject: [fixup] coccinelle issues ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/65009?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If080c1af059b7f0a9e92ea07b19562b23a9976bc Gerrit-Change-Number: 65009 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx(a)akumat.pl> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: cpu/x86/lapic: Avoid aliasing MMIO writes
by Kyösti Mälkki (Code Review) 15 Jun '23

15 Jun '23

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/55200?usp=email ) Change subject: cpu/x86/lapic: Avoid aliasing MMIO writes ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/55200?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75440cb0742eeaa140f49e7e4a4c51a96465441b Gerrit-Change-Number: 55200 Gerrit-PatchSet: 11 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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[L] Change in coreboot[master]: mb/hp: Add new port for compaq_8300_elite_usdt
by Kyösti Mälkki (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Riku Viitanen. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74906?usp=email ) Change subject: mb/hp: Add new port for compaq_8300_elite_usdt ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: I think this looks fairly ready, could you address the unresolved comments in devicetree.cb? -- To view, visit https://review.coreboot.org/c/coreboot/+/74906?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2dc31778c2aa1987d5acdf355973a203dd0bb3a3 Gerrit-Change-Number: 74906 Gerrit-PatchSet: 4 Gerrit-Owner: Riku Viitanen Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Riku Viitanen Gerrit-Comment-Date: Thu, 15 Jun 2023 08:30:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/cmd/blk/cse: Implement APIs to access FW versions in CMOS
by Subrata Banik (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Sridhar Siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74995?usp=email ) Change subject: soc/intel/cmd/blk/cse: Implement APIs to access FW versions in CMOS ...................................................................... Patch Set 36: (8 comments) File src/soc/intel/common/block/cse/Kconfig: https://review.coreboot.org/c/coreboot/+/74995/comment/beebeb12_951ff662 : PS36, Line 48: SOC_INTEL_PARTITION_FW_CMOS_OFFSET SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET ? https://review.coreboot.org/c/coreboot/+/74995/comment/567b0b24_a0a32494 : PS36, Line 53: firmware partition may be worth clarifying that its the CSE FW partition File src/soc/intel/common/block/cse/Makefile.inc: https://review.coreboot.org/c/coreboot/+/74995/comment/efd1b36f_97021189 : PS36, Line 12: i don't think any other changes are necessary here apart from adding cse_lite_cmos.c file File src/soc/intel/common/block/cse/cse_lite_cmos.c: https://review.coreboot.org/c/coreboot/+/74995/comment/05c02fc2_75d44bdd : PS36, Line 8: 0x46575054 it has to be opposite as little endian https://review.coreboot.org/c/coreboot/+/74995/comment/f0b650fa_8ba01a03 : PS36, Line 100: get_cmos_cse_version get_cmos_cse_rw_fw_version https://review.coreboot.org/c/coreboot/+/74995/comment/9fe9c87a_b4eb66ac : PS36, Line 114: set_cmos_cse_version same https://review.coreboot.org/c/coreboot/+/74995/comment/fc83b66a_ca88dca6 : PS36, Line 134: printk(BIOS_WARNING, "CMOS fw version corrupted, initiating memory re-init\n"); we don't need this IMO https://review.coreboot.org/c/coreboot/+/74995/comment/c31d8068_5694053a : PS36, Line 146: printk(BIOS_WARNING, "CMOS fw version corrupted, initiating memory re-init\n"); we don't need this -- To view, visit https://review.coreboot.org/c/coreboot/+/74995?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd0ee19575683691c0a82a291e1fd3b2ffb11786 Gerrit-Change-Number: 74995 Gerrit-PatchSet: 36 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Thu, 15 Jun 2023 08:26:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/*/root_complex: reserve IOMMU MMIO area
by Arthur Heymans (Code Review) 15 Jun '23

15 Jun '23

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75611?usp=email ) Change subject: soc/amd/*/root_complex: reserve IOMMU MMIO area ...................................................................... soc/amd/*/root_complex: reserve IOMMU MMIO area This makes sure that the resource allocator won't use this address range for anything else. In the systems I looked at, this was between the end of the above 4GB memory and the beginning of the above 4GB PCI BAR MMIO region, but better reserve it here so nothing else will get allocated there if this expectation isn't met. TEST=Reserved region is printed in the console logs: update_constraints: PCI: 00:00.0 09 base fd00000000 limit fdffffffff mem (fixed) Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5a8150873cb019ca1d903ed269e18d6f9fabb871 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75611 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/cezanne/root_complex.c M src/soc/amd/common/block/include/amdblocks/iomap.h M src/soc/amd/glinda/root_complex.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/phoenix/root_complex.c M src/soc/amd/picasso/root_complex.c 6 files changed, 23 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index 29070f6..b5bf62c 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -5,6 +5,7 @@ #include <amdblocks/alib.h> #include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> +#include <amdblocks/iomap.h> #include <amdblocks/memmap.h> #include <arch/ioapic.h> #include <arch/vga.h> @@ -151,6 +152,9 @@ gnb_apic->size = 0x00001000; gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + /* Reserve fixed IOMMU MMIO region */ + mmio_range(dev, idx++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + if (fsp_hob_iterator_init(&hob_iterator) != CB_SUCCESS) { printk(BIOS_ERR, "%s incomplete because no HOB list was found\n", __func__); diff --git a/src/soc/amd/common/block/include/amdblocks/iomap.h b/src/soc/amd/common/block/include/amdblocks/iomap.h index 759466b..d166a83 100644 --- a/src/soc/amd/common/block/include/amdblocks/iomap.h +++ b/src/soc/amd/common/block/include/amdblocks/iomap.h @@ -12,4 +12,7 @@ #define FLASH_BELOW_4GB_MAPPING_REGION_BASE ((0xffffffff - 16 * MiB) + 1) #define FLASH_BELOW_4GB_MAPPING_REGION_SIZE (16 * MiB) +#define IOMMU_RESERVED_MMIO_BASE 0xfd00000000 +#define IOMMU_RESERVED_MMIO_SIZE (4ULL * GiB) + #endif /* AMD_BLOCK_IOMAP_H */ diff --git a/src/soc/amd/glinda/root_complex.c b/src/soc/amd/glinda/root_complex.c index b18e948..1794d08 100644 --- a/src/soc/amd/glinda/root_complex.c +++ b/src/soc/amd/glinda/root_complex.c @@ -7,6 +7,7 @@ #include <amdblocks/alib.h> #include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> +#include <amdblocks/iomap.h> #include <amdblocks/memmap.h> #include <arch/ioapic.h> #include <arch/vga.h> @@ -166,6 +167,9 @@ gnb_apic->size = 0x00001000; gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + /* Reserve fixed IOMMU MMIO region */ + mmio_range(dev, idx++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + if (fsp_hob_iterator_init(&hob_iterator) != CB_SUCCESS) { printk(BIOS_ERR, "%s incomplete because no HOB list was found\n", __func__); diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 7a58f01..0dcf2b8 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -7,6 +7,7 @@ #include <amdblocks/alib.h> #include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> +#include <amdblocks/iomap.h> #include <amdblocks/memmap.h> #include <arch/ioapic.h> #include <arch/vga.h> @@ -194,6 +195,9 @@ gnb_apic->size = 0x00001000; gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + /* Reserve fixed IOMMU MMIO region */ + mmio_range(dev, idx++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + if (fsp_hob_iterator_init(&hob_iterator) != CB_SUCCESS) { printk(BIOS_ERR, "%s incomplete because no HOB list was found\n", __func__); diff --git a/src/soc/amd/phoenix/root_complex.c b/src/soc/amd/phoenix/root_complex.c index 3110ea3..a75de50 100644 --- a/src/soc/amd/phoenix/root_complex.c +++ b/src/soc/amd/phoenix/root_complex.c @@ -7,6 +7,7 @@ #include <amdblocks/alib.h> #include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> +#include <amdblocks/iomap.h> #include <amdblocks/memmap.h> #include <arch/ioapic.h> #include <arch/vga.h> @@ -166,6 +167,9 @@ gnb_apic->size = 0x00001000; gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + /* Reserve fixed IOMMU MMIO region */ + mmio_range(dev, idx++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + if (fsp_hob_iterator_init(&hob_iterator) != CB_SUCCESS) { printk(BIOS_ERR, "%s incomplete because no HOB list was found\n", __func__); diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index cd10fdb..bf36f6dd 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -6,6 +6,7 @@ #include <amdblocks/data_fabric.h> #include <amdblocks/memmap.h> #include <amdblocks/ioapic.h> +#include <amdblocks/iomap.h> #include <arch/ioapic.h> #include <arch/vga.h> #include <assert.h> @@ -149,6 +150,9 @@ gnb_apic->size = 0x00001000; gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + /* Reserve fixed IOMMU MMIO region */ + mmio_range(dev, idx++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + if (fsp_hob_iterator_init(&hob_iterator) != CB_SUCCESS) { printk(BIOS_ERR, "%s incomplete because no HOB list was found\n", __func__); return; -- To view, visit https://review.coreboot.org/c/coreboot/+/75611?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a8150873cb019ca1d903ed269e18d6f9fabb871 Gerrit-Change-Number: 75611 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/*/root_complex: reserve IOMMU MMIO area
by Arthur Heymans (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75611?usp=email ) Change subject: soc/amd/*/root_complex: reserve IOMMU MMIO area ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/common/block/include/amdblocks/iomap.h: https://review.coreboot.org/c/coreboot/+/75611/comment/4bb51a04_c6664eb7 : PS4, Line 15: 0xfd00000000 > hmm, i'd need to have a closer look at this next week. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75611?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a8150873cb019ca1d903ed269e18d6f9fabb871 Gerrit-Change-Number: 75611 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 15 Jun 2023 08:20:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/*/root_complex: reserve IOMMU MMIO area
by Arthur Heymans (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75611?usp=email ) Change subject: soc/amd/*/root_complex: reserve IOMMU MMIO area ...................................................................... Patch Set 4: Code-Review+2 (1 comment) Patchset: PS4: I found the following in docs. I guess reserving the full 4G is a good idea. If IOMMU is enabled, the processor must reserve the following addresses: • 0x00FD_0000_0000->0x00FD_F8FF_FFFF (3.9GB) • 0x00FD_F910_0000->0x00FD_F91F_FFFF (1MB) • 0x00FD_FB00_0000->0x00FD_FFFF_FFFF (80MB) -- To view, visit https://review.coreboot.org/c/coreboot/+/75611?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a8150873cb019ca1d903ed269e18d6f9fabb871 Gerrit-Change-Number: 75611 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 15 Jun 2023 08:19:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit June 2023