coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: mb/google/rex/var/screebo: rp0/rp2 change to rp1/rp3
by Subrata Banik (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Eric Lai, Kapil Porwal, Rui Zhou, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75832?usp=email ) Change subject: mb/google/rex/var/screebo: rp0/rp2 change to rp1/rp3 ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75832?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1013d26c705f2a3f9378d944bd863d94f319d36c Gerrit-Change-Number: 75832 Gerrit-PatchSet: 6 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 15 Jun 2023 13:20:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/rex/var/screebo: rp0/rp2 change to rp1/rp3
by Subrata Banik (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Eric Lai, Kapil Porwal, Rui Zhou, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75832?usp=email ) Change subject: mb/google/rex/var/screebo: rp0/rp2 change to rp1/rp3 ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > @Subrata, probably we should change TBT to 1..4 not 0..3 to match the TCSS usb? i agree. please feel free to submit the cl -- To view, visit https://review.coreboot.org/c/coreboot/+/75832?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1013d26c705f2a3f9378d944bd863d94f319d36c Gerrit-Change-Number: 75832 Gerrit-PatchSet: 6 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 15 Jun 2023 13:20:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [WIP] src/console: Replace to mutex as printk serialization
by Kyösti Mälkki (Code Review) 15 Jun '23

15 Jun '23

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/60280?usp=email ) Change subject: [WIP] src/console: Replace to mutex as printk serialization ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/60280?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5a48afe40ca86e55e91a00b8a4ee31da09fb9cb Gerrit-Change-Number: 60280 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[master]: [RFC] smp/spinlock: Use compiler builtins
by Kyösti Mälkki (Code Review) 15 Jun '23

15 Jun '23

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/60253?usp=email ) Change subject: [RFC] smp/spinlock: Use compiler builtins ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/60253?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6694784aa0810cd877886ef95434f62e3aefce6c Gerrit-Change-Number: 60253 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[master]: [WIP] intel/fsp2_0: Move fsps_load() call-site
by Kyösti Mälkki (Code Review) 15 Jun '23

15 Jun '23

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/50595?usp=email ) Change subject: [WIP] intel/fsp2_0: Move fsps_load() call-site ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/50595?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a3bc9ec412b805bc206f25be5013f7df4c018c3 Gerrit-Change-Number: 50595 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[master]: [WIP] ChromeOS: Move watchdog_tombstone and TPM reset triggers
by Kyösti Mälkki (Code Review) 15 Jun '23

15 Jun '23

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/50879?usp=email ) Change subject: [WIP] ChromeOS: Move watchdog_tombstone and TPM reset triggers ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/50879?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40b72cd63b051a2649ff450f50946e5a0a00ed4f Gerrit-Change-Number: 50879 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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[XS] Change in coreboot[master]: soc/intel/apollolake: Switch to snake case for SataPwrOptimizeDisable
by Mario Scheithauer (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Sean Rhodes. Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75859?usp=email ) Change subject: soc/intel/apollolake: Switch to snake case for SataPwrOptimizeDisable ...................................................................... soc/intel/apollolake: Switch to snake case for SataPwrOptimizeDisable For a unification of the naming convension, change from pascal case to snake case style for parameter 'SataPwrOptimizeDisable'. Change-Id: I35b36f60d2f00bfad307dff7bd131c20ebccf60b Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/75859/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 44daa5e..0e54fd8 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -745,7 +745,7 @@ } /* Sata Power Optimisation */ - silconfig->SataPwrOptEnable = !(cfg->SataPwrOptimizeDisable); + silconfig->SataPwrOptEnable = !(cfg->sata_pwr_optimize_disable); /* 8254 Timer */ bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index d43f3f0..378fccb 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -224,7 +224,7 @@ uint8_t disable_sata_salp_support; /* Sata Power Optimisation */ - uint8_t SataPwrOptimizeDisable; + uint8_t sata_pwr_optimize_disable; /* SATA speed limit */ enum sata_speed_limit sata_speed; -- To view, visit https://review.coreboot.org/c/coreboot/+/75859?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35b36f60d2f00bfad307dff7bd131c20ebccf60b Gerrit-Change-Number: 75859 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/apollolake: Switch to snake case for DisableSataSalpSupport
by Mario Scheithauer (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Sean Rhodes, Werner Zeh. Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75858?usp=email ) Change subject: soc/intel/apollolake: Switch to snake case for DisableSataSalpSupport ...................................................................... soc/intel/apollolake: Switch to snake case for DisableSataSalpSupport For a unification of the naming convension, change from pascal case to snake case style for parameter 'DisableSataSalpSupport'. Change-Id: I4a68ffd2b68c92434da681b5e5567329c8784c72 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 9 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/75858/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb index 5d4acd8..e5544a1 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb @@ -71,7 +71,7 @@ device pci 12.0 on # - SATA register "sata_ports_enable[0]" = "1" register "sata_ports_enable[1]" = "1" - register "DisableSataSalpSupport" = "1" + register "disable_sata_salp_support" = "1" end device pci 13.0 on # - RP 2 - PCIe A 0 - MACPHY register "pcie_rp_clkreq_pin[2]" = "0" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index 7054413..ae9c3b1 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -71,7 +71,7 @@ register "sata_ports_enable[1]" = "1" register "sata_ports_ssd[0]" = "1" register "sata_ports_ssd[1]" = "1" - register "DisableSataSalpSupport" = "1" + register "disable_sata_salp_support" = "1" register "sata_speed" = "SATA_GEN2" end device pci 13.0 on # - RP 2 - PCIe A 0 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb index 472f5ba..74e30bb 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -66,7 +66,7 @@ device pci 12.0 on # - SATA register "sata_ports_enable[0]" = "1" register "sata_ports_enable[1]" = "1" - register "DisableSataSalpSupport" = "1" + register "disable_sata_salp_support" = "1" end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index baaff1e..e5d80be 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -60,7 +60,7 @@ device pci 12.0 on # - SATA register "sata_ports_enable[0]" = "1" register "sata_ports_enable[1]" = "1" - register "DisableSataSalpSupport" = "1" + register "disable_sata_salp_support" = "1" end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index 52fcd49..87e4cc2 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -71,7 +71,7 @@ register "sata_ports_enable[1]" = "1" register "sata_ports_ssd[0]" = "1" register "sata_ports_ssd[1]" = "1" - register "DisableSataSalpSupport" = "1" + register "disable_sata_salp_support" = "1" register "sata_speed" = "SATA_GEN2" end device pci 13.0 on # - RP 2 - PCIe A 0 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index dc66be6..86e92d5 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -42,7 +42,7 @@ register "sata_ports_enable[1]" = "1" register "sata_ports_ssd[0]" = "1" register "sata_ports_ssd[1]" = "1" - register "DisableSataSalpSupport" = "1" + register "disable_sata_salp_support" = "1" register "sata_speed" = "SATA_GEN2" end device pci 13.0 on # - RP 2 - PCIe A 0 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb index 0a080c3..6cf285f 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb @@ -58,7 +58,7 @@ device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on # - SATA - register "DisableSataSalpSupport" = "1" + register "disable_sata_salp_support" = "1" end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 5f9b346..44daa5e 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -736,7 +736,7 @@ /* SATA config */ if (is_devfn_enabled(PCH_DEVFN_SATA)) { - silconfig->SataSalpSupport = !(cfg->DisableSataSalpSupport); + silconfig->SataSalpSupport = !(cfg->disable_sata_salp_support); ahci_set_speed(cfg->sata_speed); memcpy(silconfig->SataPortsEnable, cfg->sata_ports_enable, sizeof(silconfig->SataPortsEnable)); diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 2d6b079..d43f3f0 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -221,7 +221,7 @@ uint8_t disable_xhci_lfps_pm; /* SATA Aggressive Link Power Management */ - uint8_t DisableSataSalpSupport; + uint8_t disable_sata_salp_support; /* Sata Power Optimisation */ uint8_t SataPwrOptimizeDisable; -- To view, visit https://review.coreboot.org/c/coreboot/+/75858?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a68ffd2b68c92434da681b5e5567329c8784c72 Gerrit-Change-Number: 75858 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: soc/intel/apollolake: Switch to snake case for PmicVdd2Voltage
by Mario Scheithauer (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Sean Rhodes. Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75857?usp=email ) Change subject: soc/intel/apollolake: Switch to snake case for PmicVdd2Voltage ...................................................................... soc/intel/apollolake: Switch to snake case for PmicVdd2Voltage For a unification of the naming convension, change from pascal case to snake case style for parameter 'PmicVdd2Voltage'. Change-Id: I179b8f5b56c5bfe7f6fc3148e4c95954c0755ffd Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/75857/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 956a55b..5f9b346 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -622,7 +622,7 @@ /* * Options to adjust PMIC Vdd2 voltage. */ - silconfig->PmicVdd2Voltage = cfg->PmicVdd2Voltage; + silconfig->PmicVdd2Voltage = cfg->pmic_vdd2_voltage; /* FSP should let coreboot set subsystem IDs, which are read/write-once */ silconfig->SiSVID = 0; diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 5a3aa88..2d6b079 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -204,7 +204,7 @@ * + OR Value (15:8) + AND Value (7:0) through BUCK5_VID[3:2]: * 00=1.10v, 01=1.15v, 10=1.24v, 11=1.20v (default). */ - uint32_t PmicVdd2Voltage; + uint32_t pmic_vdd2_voltage; /* Option to enable VTD feature. Default is 0 which disables VTD * capability in FSP. Setting this option to 1 in devicetree will enable -- To view, visit https://review.coreboot.org/c/coreboot/+/75857?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I179b8f5b56c5bfe7f6fc3148e4c95954c0755ffd Gerrit-Change-Number: 75857 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: soc/intel/apollolake: Switch to snake case for ModPhyVoltageBump
by Mario Scheithauer (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Sean Rhodes. Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75856?usp=email ) Change subject: soc/intel/apollolake: Switch to snake case for ModPhyVoltageBump ...................................................................... soc/intel/apollolake: Switch to snake case for ModPhyVoltageBump For a unification of the naming convension, change from pascal case to snake case style for parameter 'ModPhyVoltageBump'. Change-Id: Ic1e743e23bdfc45588411c584eecb839cc552faf Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/75856/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index a29ba3b..956a55b 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -617,7 +617,7 @@ /* * Options to bump USB3 LDO voltage with 40mv. */ - silconfig->ModPhyVoltageBump = cfg->ModPhyVoltageBump; + silconfig->ModPhyVoltageBump = cfg->mod_phy_voltage_bump; /* * Options to adjust PMIC Vdd2 voltage. diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 26e4478..5a3aa88 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -196,7 +196,7 @@ * LDO voltage. Set TRUE to increase LDO voltage with 40mV. * 0:FALSE (default), 1:True. */ - uint8_t ModPhyVoltageBump; + uint8_t mod_phy_voltage_bump; /* Options to adjust PMIC Vdd2 voltage. Default is 0 to not adjusting * the PMIC Vdd2 default voltage 1.20v. Upd for changing Vdd2 Voltage -- To view, visit https://review.coreboot.org/c/coreboot/+/75856?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1e743e23bdfc45588411c584eecb839cc552faf Gerrit-Change-Number: 75856 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: newchange

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coreboot-gerrit June 2023