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ChiaLing has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75680?usp=email )
Change subject: mb/google/dedede: Support variant specific power limits
......................................................................
Patch Set 11:
(2 comments)
File src/mainboard/google/dedede/variants/baseboard/ramstage.c:
https://review.coreboot.org/c/coreboot/+/75680/comment/c1fa077a_cd31252c :
PS10, Line 18: WATT_CONVERTER
> nit: MICROWATTS_TO_WATTS
Done
https://review.coreboot.org/c/coreboot/+/75680/comment/6460aded_dd1bbee1 :
PS10, Line 80: W
> Move the unit inside the brackets
Done
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Hello Reka Norman, Ryan Lin, Subrata Banik, Zhuohao Lee, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/google/dedede: Support variant specific power limits
......................................................................
mb/google/dedede: Support variant specific power limits
With newer dedede design, it's required to config corresponding
psyspmax, psyspl1, psyspl2, pl1 and pl2 by different kinds of
adapter.
BUG=b:281479111
TEST=emerge-dedede coreboot and check correct value on dibbi
Signed-off-by: Chia-Ling Hou <chia-ling.hou(a)intel.com>
Change-Id: I583c930379233322c41027805369f81d02000ee7
---
M src/mainboard/google/dedede/variants/baseboard/Makefile.inc
M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h
A src/mainboard/google/dedede/variants/baseboard/ramstage.c
3 files changed, 108 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/75680/11
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Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75737?usp=email )
Change subject: lib/smbios: Add a config string for BIOS Vendor in SMBIOS Type 0
......................................................................
lib/smbios: Add a config string for BIOS Vendor in SMBIOS Type 0
BIOS Vendor in SMBIOS Type 0 would be who built the firmware so create a
config string with default "coreboot" to make it changeable. Vendors
could update it by adding a Kconfig in the site-local directory.
Change-Id: I6dfcca338ffc48b150c966b9aefcefe928704d24
Signed-off-by: Yiwei Tang <tangyiwei.2022(a)bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75737
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
---
M src/Kconfig
M src/lib/smbios.c
2 files changed, 8 insertions(+), 1 deletion(-)
Approvals:
Eric Lai: Looks good to me, but someone else must approve
Felix Singer: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/Kconfig b/src/Kconfig
index 8e72f2d..f5ba4fc 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -891,6 +891,13 @@
if GENERATE_SMBIOS_TABLES
+config BIOS_VENDOR
+ prompt "SMBIOS BIOS Vendor name"
+ string
+ default "coreboot"
+ help
+ The BIOS Vendor name to store in the SMBIOS Type0 table.
+
config MAINBOARD_SERIAL_NUMBER
prompt "SMBIOS Serial Number" if !SMBIOS_PROVIDED_BY_MOBO
string
diff --git a/src/lib/smbios.c b/src/lib/smbios.c
index 3b3360c..deee193b 100644
--- a/src/lib/smbios.c
+++ b/src/lib/smbios.c
@@ -371,7 +371,7 @@
struct smbios_type0 *t = smbios_carve_table(*current, SMBIOS_BIOS_INFORMATION,
sizeof(*t), handle);
- t->vendor = smbios_add_string(t->eos, "coreboot");
+ t->vendor = smbios_add_string(t->eos, CONFIG_BIOS_VENDOR);
t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date);
if (CONFIG(CHROMEOS_NVS)) {
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Change subject: lib/smbios: Add a config string for BIOS Vendor in SMBIOS Type 0
......................................................................
Patch Set 6: Code-Review+1
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Change subject: lib/smbios: Add a config string for BIOS Vendor in SMBIOS Type 0
......................................................................
Patch Set 6: Code-Review+2
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Hello Angel Pons, Arthur Heymans, Eric Lai, Felix Held, Felix Singer, Jeff Li, Johnny Lin, Jonathan Zhang, Kyösti Mälkki, Lean Sheng Tan, Martin Roth, Nill Ge, Subrata Banik, Ziang Wang, build bot (Jenkins), niehaitao(a)bytedance.com,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#6).
The following approvals got outdated and were removed:
Code-Review+1 by Felix Held, Code-Review+1 by Felix Singer, Code-Review+1 by Kyösti Mälkki, Verified+1 by build bot (Jenkins)
Change subject: lib/smbios: Add a config string for BIOS Vendor in SMBIOS Type 0
......................................................................
lib/smbios: Add a config string for BIOS Vendor in SMBIOS Type 0
BIOS Vendor in SMBIOS Type 0 would be who built the firmware so create a
config string with default "coreboot" to make it changeable. Vendors
could update it by adding a Kconfig in the site-local directory.
Change-Id: I6dfcca338ffc48b150c966b9aefcefe928704d24
Signed-off-by: Yiwei Tang <tangyiwei.2022(a)bytedance.com>
---
M src/Kconfig
M src/lib/smbios.c
2 files changed, 8 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/75737/6
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The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: mb/google/rex: Avoid LPDDR5/x hang
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76076/comment/54514958_762f7452 :
PS1, Line 9: avoids hang observed
Under which circumstances does this happen?
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Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75818?usp=email )
(
6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: soc/mediatek: Enable DRAM scramble on fast calibration flow
......................................................................
soc/mediatek: Enable DRAM scramble on fast calibration flow
No matter what DRAM calibration is performed, DRAM scramble should be
enabled as long as MEDIATEK_DRAM_SCRAMBLE is set to y. Currently, DRAM
scramble is enabled only if full calibration is performed. Correct the
behavior by adding DRAMC_CONFIG_SCRAMBLE to the header config in fast
calibration flow.
BUG=b:285474337
TEST=Check the scramble feature is disabled on serial build
Signed-off-by: Xi Chen <xixi.chen(a)mediatek.corp-partner.google.com>
Change-Id: I907bccd4e68e040179e1971db6bf7a57b88dec1b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75818
Reviewed-by: Yu-Ping Wu <yupingso(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/mediatek/common/memory.c
1 file changed, 2 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Yu-Ping Wu: Looks good to me, approved
diff --git a/src/soc/mediatek/common/memory.c b/src/soc/mediatek/common/memory.c
index b6f7dde..1a627dd 100644
--- a/src/soc/mediatek/common/memory.c
+++ b/src/soc/mediatek/common/memory.c
@@ -202,6 +202,8 @@
printk(BIOS_INFO, "DRAM-K: DRAM calibration data valid pass\n");
+ if (CONFIG(MEDIATEK_DRAM_SCRAMBLE))
+ dparam->header.config |= DRAMC_CONFIG_SCRAMBLE;
if (CONFIG(MEDIATEK_DRAM_BLOB_FAST_INIT)) {
printk(BIOS_INFO, "DRAM-K: Run fast calibration run in blob mode\n");
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Change subject: mb/google/rex: Avoid LPDDR5/x hang
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/nissa/var/gothrax: Add GPIO table for gothrax
......................................................................
Patch Set 6: Code-Review-1
(1 comment)
File src/mainboard/google/brya/variants/gothrax/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/75872/comment/e45387b8_cad47e28 :
PS6, Line 4: romstage-y += memory.c
There is no memory.c exist, is it buildable?
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