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Change subject: util/docker/coreboot-sdk: Install GNAT meta package instead gnat-12
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Patch Set 1: Code-Review+2
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Change subject: mb/google/rex: Enable Bluetooth offload for soundwire audio
......................................................................
Patch Set 9:
(1 comment)
Patchset:
PS9:
> This is mentioned as SSP1 in the commit message contains "This patch enables BT offload feature for […]
Related OS changes are under review
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Change subject: mb/google/rex: Enable Bluetooth offload for soundwire audio
......................................................................
Patch Set 9:
(1 comment)
Patchset:
PS9:
> .
This is mentioned as SSP1 in the commit message contains "This patch enables BT offload feature for soundwire audio over SSP1".
Please let me know, if you need explicit mention of I2S in this - i can update the commit message to "Enable Bluetooth I2S offload for soundwire audio"?
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Change subject: mb/google/rex: Enable Bluetooth offload for soundwire audio
......................................................................
Patch Set 9:
(1 comment)
Patchset:
PS9:
Looks good.
Can we also mention that this feature has nothing to do with soundwire itself? Here we are enabling BT offload over I2S while having SNDW DB connected.
Do we already have corresponding changes in the OS?
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Change subject: mb/google/rex: Avoid LPDDR5/x hang
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76076/comment/eff9431a_7e12a88b :
PS1, Line 9: avoids hang observed
> Under which circumstances does this happen?
random hang after booting to OS
updated the commit msg now
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Change subject: mb/google/rex: Avoid LPDDR5/x hang
......................................................................
mb/google/rex: Avoid LPDDR5/x hang
This patch avoids random hang issue observed after booted to OS on LPDD5/x platforms due to CLK not tuned properly in SAGV point 0, 2133MT/s.
As per Intel doc 769410 the expected work around is to change SAGV
point 0 from 2133 G4 to 3200 G4.
BUG=b:287170545
TEST=Able to perform 500 power cycles on google/rex without any hang.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I02a9cadc075f396549703d7a008382e76268f865
---
M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/76076/3
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Hello Eric Lai, Jakub Czapiga, Kapil Porwal, Tarun Tuli, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/rex: Avoid LPDDR5/x hang
......................................................................
mb/google/rex: Avoid LPDDR5/x hang
This patch avoids random hang observed on LPDD5/x platforms due to
CLK not tuned properly in SAGV point 0, 2133MT/s.
As per Intel doc 769410 the expected work around is to change SAGV
point 0 from 2133 G4 to 3200 G4.
BUG=b:287170545
TEST=Able to perform 500 power cycles on google/rex without any hang.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I02a9cadc075f396549703d7a008382e76268f865
---
M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/76076/2
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Change subject: nb/intel/pineview: Drop unused attributes from sysinfo struct
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Patch Set 2: Code-Review+2
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Change subject: mb/google/nissa/var/gothrax: Add GPIO table for gothrax
......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/google/brya/variants/gothrax/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/75872/comment/331dad73_07b27d7d :
PS6, Line 4: romstage-y += memory.c
> There is no memory. […]
Don't submit this file anymore, forgot to modify it here.
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