coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: acpi/acpigen.c: Be explicit about char sign
by Felix Held (Code Review) 26 Jun '23

26 Jun '23

Attention is currently required from: Arthur Heymans, Lance Zhao, Tim Wawrzynczak. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76006?usp=email ) Change subject: acpi/acpigen.c: Be explicit about char sign ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/76006/comment/1d00b34a_3cc9fed1 : PS1, Line 9: is architecture : dependent huh, i didn't expect this to be the case -- To view, visit https://review.coreboot.org/c/coreboot/+/76006?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53b99835b2ffec5d752fc531fd59e4715f61aced Gerrit-Change-Number: 76006 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 26 Jun 2023 12:05:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/common/block/acpi/ivrs: zero-initialize ivhd_[range,entry]
by Felix Held (Code Review) 26 Jun '23

26 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76079?usp=email ) Change subject: soc/amd/common/block/acpi/ivrs: zero-initialize ivhd_[range,entry] ...................................................................... soc/amd/common/block/acpi/ivrs: zero-initialize ivhd_[range,entry] Zero-initialize the ivhd_range and ivhd_entry structs to make sure that the whole struct is in a defined state. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iccacc89bfc497449ad0716a3436949505b65f748 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76079 Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/acpi/ivrs.c 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index 71b9c62..089b42d 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -69,6 +69,7 @@ /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ current = ALIGN_UP(current, 4); ivrs_ivhd_generic_t *ivhd_range = (ivrs_ivhd_generic_t *)current; + memset(ivhd_range, 0, sizeof(*ivhd_range)); /* Create the start range IVHD entry */ ivhd_range->type = IVHD_DEV_4_BYTE_START_RANGE; @@ -93,6 +94,7 @@ /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ *current = ALIGN_UP(*current, 4); ivrs_ivhd_generic_t *ivhd_entry = (ivrs_ivhd_generic_t *)*current; + memset(ivhd_entry, 0, sizeof(*ivhd_entry)); ivhd_entry->type = type; ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); @@ -100,6 +102,7 @@ *current += sizeof(ivrs_ivhd_generic_t); } else if (type == IVHD_DEV_8_BYTE_ALIAS_SELECT) { ivrs_ivhd_alias_t *ivhd_entry = (ivrs_ivhd_alias_t *)*current; + memset(ivhd_entry, 0, sizeof(*ivhd_entry)); ivhd_entry->type = type; ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); -- To view, visit https://review.coreboot.org/c/coreboot/+/76079?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccacc89bfc497449ad0716a3436949505b65f748 Gerrit-Change-Number: 76079 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: soc/amd/common/block/acpi/ivrs: use size of instance instead of type
by Felix Held (Code Review) 26 Jun '23

26 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76078?usp=email ) Change subject: soc/amd/common/block/acpi/ivrs: use size of instance instead of type ...................................................................... soc/amd/common/block/acpi/ivrs: use size of instance instead of type To determine the length parameter of memset, use sizeof with the instance as argument instead of the type. The behavior is the same, but it clarifies parameters in the memset call a bit. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I63674fbed7097a583cd77fa6e700652d6dcc5565 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76078 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/common/block/acpi/ivrs.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Fred Reitberger: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index d5a409f..71b9c62 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -203,7 +203,7 @@ acpi_ivrs_ivhd40_t *ivhd_40 = (acpi_ivrs_ivhd40_t *)current; unsigned long current_backup; - memset(ivhd_40, 0, sizeof(acpi_ivrs_ivhd40_t)); + memset(ivhd_40, 0, sizeof(*ivhd_40)); /* Enable EFR */ ivhd_40->type = IVHD_BLOCK_TYPE_FULL__ACPI_HID; @@ -260,7 +260,7 @@ * In order to utilize all features, firmware should expose type 11h * IVHD which supersedes the type 10h. */ - memset(ivhd_11, 0, sizeof(acpi_ivrs_ivhd11_t)); + memset(ivhd_11, 0, sizeof(*ivhd_11)); /* Enable EFR */ ivhd_11->type = IVHD_BLOCK_TYPE_FULL__FIXED; -- To view, visit https://review.coreboot.org/c/coreboot/+/76078?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63674fbed7097a583cd77fa6e700652d6dcc5565 Gerrit-Change-Number: 76078 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/common/block/acpi/ivrs: use memset on ivhd_[11,40]
by Felix Held (Code Review) 26 Jun '23

26 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76077?usp=email ) Change subject: soc/amd/common/block/acpi/ivrs: use memset on ivhd_[11,40] ...................................................................... soc/amd/common/block/acpi/ivrs: use memset on ivhd_[11,40] Assign the current address casted to acpi_ivrs_ivhd[11,40]_t pointer to *ivhd_[11,40] at the beginning of acpi_fill_ivrs[11,40] and then use memset on *ivhd_[11,40] to zero-initialize the structs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I70b12fee99d6c71318189ac35e615589a4c8c629 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76077 Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/acpi/ivrs.c 1 file changed, 4 insertions(+), 6 deletions(-) Approvals: Fred Reitberger: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index d2080e9..d5a409f 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -200,11 +200,10 @@ static unsigned long acpi_fill_ivrs40(unsigned long current, acpi_ivrs_ivhd_t *ivhd, struct device *nb_dev, struct device *iommu_dev) { - acpi_ivrs_ivhd40_t *ivhd_40; + acpi_ivrs_ivhd40_t *ivhd_40 = (acpi_ivrs_ivhd40_t *)current; unsigned long current_backup; - memset((void *)current, 0, sizeof(acpi_ivrs_ivhd40_t)); - ivhd_40 = (acpi_ivrs_ivhd40_t *)current; + memset(ivhd_40, 0, sizeof(acpi_ivrs_ivhd40_t)); /* Enable EFR */ ivhd_40->type = IVHD_BLOCK_TYPE_FULL__ACPI_HID; @@ -253,7 +252,7 @@ static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_ivhd_t *ivhd, struct device *nb_dev, struct device *iommu_dev) { - acpi_ivrs_ivhd11_t *ivhd_11; + acpi_ivrs_ivhd11_t *ivhd_11 = (acpi_ivrs_ivhd11_t *)current; ivhd11_iommu_attr_t *ivhd11_attr_ptr; unsigned long current_backup; @@ -261,8 +260,7 @@ * In order to utilize all features, firmware should expose type 11h * IVHD which supersedes the type 10h. */ - memset((void *)current, 0, sizeof(acpi_ivrs_ivhd11_t)); - ivhd_11 = (acpi_ivrs_ivhd11_t *)current; + memset(ivhd_11, 0, sizeof(acpi_ivrs_ivhd11_t)); /* Enable EFR */ ivhd_11->type = IVHD_BLOCK_TYPE_FULL__FIXED; -- To view, visit https://review.coreboot.org/c/coreboot/+/76077?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70b12fee99d6c71318189ac35e615589a4c8c629 Gerrit-Change-Number: 76077 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: mb/google/rex: Set TCC to 90°C
by Sumeet R Pawnikar (Code Review) 26 Jun '23

26 Jun '23

Attention is currently required from: Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun Tuli. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76110?usp=email ) Change subject: mb/google/rex: Set TCC to 90°C ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/76110/comment/fbf45270_e670782f : PS2, Line 8: > mb/google/rex: Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76110?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0567b6240fcb53f38158c381b700169475cf3795 Gerrit-Change-Number: 76110 Gerrit-PatchSet: 3 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 26 Jun 2023 11:48:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/rex: Set TCC to 90°C
by Sumeet R Pawnikar (Code Review) 26 Jun '23

26 Jun '23

Attention is currently required from: Jakub Czapiga, Kapil Porwal, Subrata Banik, Sumeet R Pawnikar, Tarun Tuli. Hello Eric Lai, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76110?usp=email to look at the new patch set (#3). Change subject: mb/google/rex: Set TCC to 90°C ...................................................................... mb/google/rex: Set TCC to 90°C Set tcc_offset value to 20 in devicetree for Thermal Control Circuit (TCC) activation feature for rex variants. BUG=b:270664854 BRANCH=None TEST=Build FW and test on rex board Change-Id: I0567b6240fcb53f38158c381b700169475cf3795 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/76110/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/76110?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0567b6240fcb53f38158c381b700169475cf3795 Gerrit-Change-Number: 76110 Gerrit-PatchSet: 3 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: mb/google/rex/var/baseboard/rex: Set TCC to 90°C
by Eric Lai (Code Review) 26 Jun '23

26 Jun '23

Attention is currently required from: Jakub Czapiga, Kapil Porwal, Subrata Banik, Sumeet R Pawnikar, Tarun Tuli. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76110?usp=email ) Change subject: mb/google/rex/var/baseboard/rex: Set TCC to 90°C ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/76110/comment/401d3f84_983c11cb : PS2, Line 8: mb/google/rex: -- To view, visit https://review.coreboot.org/c/coreboot/+/76110?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0567b6240fcb53f38158c381b700169475cf3795 Gerrit-Change-Number: 76110 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Mon, 26 Jun 2023 11:28:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/rex/var/baseboard/rex: Set TCC to 90°C
by Eric Lai (Code Review) 26 Jun '23

26 Jun '23

Attention is currently required from: Jakub Czapiga, Kapil Porwal, Subrata Banik, Sumeet R Pawnikar, Tarun Tuli. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76110?usp=email ) Change subject: mb/google/rex/var/baseboard/rex: Set TCC to 90°C ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76110?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0567b6240fcb53f38158c381b700169475cf3795 Gerrit-Change-Number: 76110 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Mon, 26 Jun 2023 11:27:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/common/block/pci: Generalise irq base calculation
by Naresh Solanki (Code Review) 26 Jun '23

26 Jun '23

Naresh Solanki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76103?usp=email ) Change subject: soc/amd/common/block/pci: Generalise irq base calculation ...................................................................... soc/amd/common/block/pci: Generalise irq base calculation Generalize IRQ base calculation for multiple IOMMU IO-APIC scenario. Signed-off-by: Naresh Solanki <Naresh.Solanki(a)9elements.com> Change-Id: I2a8c4b54d7aa3d834cb8d86ee1ca10d7cd149b93 --- M src/soc/amd/common/block/pci/acpi_prt.c 1 file changed, 26 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/76103/1 diff --git a/src/soc/amd/common/block/pci/acpi_prt.c b/src/soc/amd/common/block/pci/acpi_prt.c index f748024..20e01a0 100644 --- a/src/soc/amd/common/block/pci/acpi_prt.c +++ b/src/soc/amd/common/block/pci/acpi_prt.c @@ -4,25 +4,23 @@ #include <acpi/acpigen.h> #include <acpi/acpigen_pci.h> #include <amdblocks/amd_pci_util.h> +#include <amdblocks/data_fabric.h> #include <arch/ioapic.h> #include <device/device.h> -/* GNB IO-APIC is located after the FCH IO-APIC */ -#define FCH_IOAPIC_INTERRUPTS 24 -#define GNB_GSI_BASE FCH_IOAPIC_INTERRUPTS - -static void acpigen_write_PRT_GSI(const struct pci_routing_info *routing_info) +static void acpigen_write_PRT_GSI(uint16_t gsi_irq_base, const struct pci_routing_info *routing_info) { unsigned int irq; acpigen_write_package(4); /* Package - APIC Routing */ for (unsigned int i = 0; i < 4; ++i) { - irq = pci_calculate_irq(routing_info, i); + irq = gsi_irq_base; + irq += pci_calculate_irq(routing_info, i); acpigen_write_PRT_GSI_entry( 0, /* There is only one device attached to the bridge */ i, /* pin */ - GNB_GSI_BASE + irq); + irq); } acpigen_pop_len(); /* Package - APIC Routing */ } @@ -131,10 +129,30 @@ { const struct pci_routing_info *routing_info = get_pci_routing_info(dev->path.pci.devfn); + struct device *domain = NULL; + struct resource *res; + uint16_t gsi_irq_base; if (!routing_info) return; + /* GNB IO-APIC is located after the FCH IO-APIC */ + gsi_irq_base = ioapic_get_max_vectors(VIO_APIC_VADDR); + + /* IRQs in the presence of multiple IOMMU IO-APICs */ + while ((domain = dev_find_path(domain, DEVICE_PATH_DOMAIN)) != NULL) { + + if (domain->link_list == dev->bus ) + break; + + res = probe_resource(domain, IOMMU_IOAPIC_IDX); + if (!res) + continue; + + gsi_irq_base += ioapic_get_max_vectors((u8 *)(uintptr_t)res->base); + } + printk(BIOS_DEBUG, "%s -> irq base: %x\n", dev_path(dev), gsi_irq_base); + acpigen_write_method("_PRT", 0); /* If (PICM) */ @@ -143,7 +161,7 @@ /* Return (Package{...}) */ acpigen_emit_byte(RETURN_OP); - acpigen_write_PRT_GSI(routing_info); + acpigen_write_PRT_GSI(gsi_irq_base, routing_info); /* Else */ acpigen_write_else(); -- To view, visit https://review.coreboot.org/c/coreboot/+/76103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a8c4b54d7aa3d834cb8d86ee1ca10d7cd149b93 Gerrit-Change-Number: 76103 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: mb/google/rex/var/baseboard/rex: Set TCC to 90°C
by Sumeet R Pawnikar (Code Review) 26 Jun '23

26 Jun '23

Attention is currently required from: Eric Lai, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun Tuli. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76110?usp=email ) Change subject: mb/google/rex/var/baseboard/rex: Set TCC to 90°C ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb: https://review.coreboot.org/c/coreboot/+/76110/comment/22a02593_c17f6c61 : PS1, Line 39: Tj max > I hope `Tj Max` is 110C ? […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76110?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0567b6240fcb53f38158c381b700169475cf3795 Gerrit-Change-Number: 76110 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 26 Jun 2023 11:19:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit June 2023