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Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs
......................................................................
Patch Set 12:
(1 comment)
File src/mainboard/bytedance/bd_egs/Kconfig:
https://review.coreboot.org/c/coreboot/+/75722/comment/fbd7d27c_95ae7b81 :
PS10, Line 32: default "\\_SB.C%03d"
> is there any acpi bytecode that gets emitted by the fsp that references the cpu object or are all re […]
Hi Yiwei, could you check if you remove this line will it still works on your side?
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Change subject: mb/google/rex: Set TCC to 90°C
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Patch Set 3: Code-Review+2
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Change subject: mb/google/rex: Avoid LPDDR5/x hang
......................................................................
mb/google/rex: Avoid LPDDR5/x hang
This patch avoids random hang issue observed after booted to OS on LPDD5/x platforms due to CLK not tuned properly in SAGV point 0, 2133MT/s.
As per Intel doc 769410 the expected work around is to change SAGV
point 0 from 2133 G4 to 3200 G4.
BUG=b:287170545
TEST=Able to perform 500 power cycles on google/rex without any hang.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
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---
M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Eric Lai: Looks good to me, approved
build bot (Jenkins): Verified
Lean Sheng Tan: Looks good to me, approved
Kapil Porwal: Looks good to me, approved
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
index 5297ce2..0d639e3 100644
--- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
+++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
@@ -41,7 +41,7 @@
register "sagv" = "SAGV_ENABLED"
- register "sagv_freq_mhz[0]" = "2133"
+ register "sagv_freq_mhz[0]" = "3200"
register "sagv_gear[0]" = "4"
register "sagv_freq_mhz[1]" = "6000"
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Change subject: mb/google/dedede/var/dibbi: Update power limits
......................................................................
Patch Set 10:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75681/comment/b85a0ee0_ec6f9683 :
PS10, Line 9: limit
limit*s*?
https://review.coreboot.org/c/coreboot/+/75681/comment/c54d8055_a63e2c4f :
PS10, Line 10:
What were the default(?) limits before your change?
File src/mainboard/google/dedede/variants/dibbi/ramstage.c:
https://review.coreboot.org/c/coreboot/+/75681/comment/034df4da_ce8edbcc :
PS10, Line 6: .
Not needed.
https://review.coreboot.org/c/coreboot/+/75681/comment/072d5f9f_e2b7467b :
PS10, Line 14: b/w
I’d write between, as there are non-native readers too.
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Change subject: [WIP] include/post_code: Reorganize POST code to range specific header
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Patch Set 3:
(1 comment)
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https://review.coreboot.org/c/coreboot/+/76099/comment/0d9b75a8_01572f54 :
PS3, Line 2: lilacious
Would it be possible to use your full namee Yuchen He?
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Change subject: mb/google/rex: Enable defer CSE firmware downgrade config
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Patch Set 2:
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Change subject: mtl: Allow call to cse_fw_sync() in romstage with defer CSE downgrade config
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Change subject: include/amdblocks/post_code.h: Change post code prefix to POSTCODE
......................................................................
Patch Set 3:
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Change subject: cse: Add deferred CSE downgrade flow
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Patch Set 2:
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