coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: util/docker/coreboot-sdk: Do system update before installing packages
by Martin L Roth (Code Review) 26 Jun '23

26 Jun '23

Attention is currently required from: Felix Singer. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76081?usp=email ) Change subject: util/docker/coreboot-sdk: Do system update before installing packages ...................................................................... Patch Set 3: Code-Review-1 (1 comment) Patchset: PS3: We don't want to do this. Basing as much as possible on the base docker binary makes it more repeatable. If there were a way to install all the packages from a known specific source so that we didn't even need to run apt update, we'd prefer that as well. If there's some reason that this is needed somewhere else, we could do this there, but for the base coreboot-sdk it's not desired. -- To view, visit https://review.coreboot.org/c/coreboot/+/76081?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ae80a753cffafc849325264f4acfbf09b8d0b9a Gerrit-Change-Number: 76081 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Mon, 26 Jun 2023 17:46:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mainboard/google/rex: Enable crashlog
by Martin L Roth (Code Review) 26 Jun '23

26 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74770?usp=email ) Change subject: mainboard/google/rex: Enable crashlog ...................................................................... mainboard/google/rex: Enable crashlog Enable crashlog for rex. Select config options SOC_INTEL_CRASHLOG, and SOC_INTEL_IOE_DIE_SUPPORT. Also enable ioe_shared_sram and pmc_shared_sram devices. BUG=b:262501347 TEST=Able to trigger Crashlog, BERT table gets generated and decodes as expected. Change-Id: I3d3a9fb41d1293f021ad9de9b29c756cb7559373 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74770 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/variants/rex0/overridetree.cb 2 files changed, 4 insertions(+), 0 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index f552ef8..4bb9a67 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -25,9 +25,11 @@ select MAINBOARD_HAS_TPM2 select PMC_IPC_ACPI_INTERFACE select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT + select SOC_INTEL_CRASHLOG select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 select SOC_INTEL_CSE_SEND_EOP_ASYNC + select SOC_INTEL_IOE_DIE_SUPPORT config BOARD_GOOGLE_BASEBOARD_REX def_bool n diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 4f74ea4..bd38595 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -349,6 +349,7 @@ device generic 0 on end end end + device ref ioe_shared_sram on end device ref xhci on chip drivers/usb/acpi device ref xhci_root_hub on @@ -412,6 +413,7 @@ end end end + device ref pmc_shared_sram on end device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" -- To view, visit https://review.coreboot.org/c/coreboot/+/74770?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d3a9fb41d1293f021ad9de9b29c756cb7559373 Gerrit-Change-Number: 74770 Gerrit-PatchSet: 23 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/common: Print crashlog size info in hex
by Martin L Roth (Code Review) 26 Jun '23

26 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75910?usp=email ) Change subject: soc/intel/common: Print crashlog size info in hex ...................................................................... soc/intel/common: Print crashlog size info in hex Print crashlog size information in hex to be consistent with other prints. BUG=b:262501347 TEST=Values printed in hex. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> Change-Id: Ieb5498e702497bfbc2b4d5396d5b760a0010f5de Reviewed-on: https://review.coreboot.org/c/coreboot/+/75910 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/acpi/acpi_bert.c 1 file changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/acpi_bert.c b/src/soc/intel/common/block/acpi/acpi_bert.c index 37309de..350d5d3 100644 --- a/src/soc/intel/common/block/acpi/acpi_bert.c +++ b/src/soc/intel/common/block/acpi/acpi_bert.c @@ -56,12 +56,12 @@ if (cpu_record_size) { cl_data = new_cper_fw_error_crashlog(status, cpu_record_size); if (!cl_data) { - printk(BIOS_ERR, "Crashlog CPU entry(size %zu) " + printk(BIOS_ERR, "Crashlog CPU entry(size 0x%zx) " "would exceed available region\n", cpu_record_size); return CB_ERR; } - printk(BIOS_DEBUG, "cl_data %p, cpu_record_size %zu\n", + printk(BIOS_DEBUG, "cl_data %p, cpu_record_size 0x%zx\n", cl_data, cpu_record_size); cl_fill_cpu_records(cl_data); } @@ -77,12 +77,12 @@ cl_data = new_cper_fw_error_crashlog(status, pmc_record_size); if (!cl_data) { - printk(BIOS_ERR, "Crashlog PMC entry(size %zu) " + printk(BIOS_ERR, "Crashlog PMC entry(size 0x%zx) " "would exceed available region\n", pmc_record_size); return CB_ERR; } - printk(BIOS_DEBUG, "cl_data %p, pmc_record_size %zu\n", + printk(BIOS_DEBUG, "cl_data %p, pmc_record_size 0x%zx\n", cl_data, pmc_record_size); cl_fill_pmc_records(cl_data); } @@ -99,12 +99,12 @@ cl_data = new_cper_fw_error_crashlog(status, ioe_record_size); if (!cl_data) { - printk(BIOS_ERR, "Crashlog IOE entry(size %zu) " + printk(BIOS_ERR, "Crashlog IOE entry(size 0x%zx) " "would exceed available region\n", ioe_record_size); return CB_ERR; } - printk(BIOS_DEBUG, "cl_data %p, ioe_record_size %zu\n", + printk(BIOS_DEBUG, "cl_data %p, ioe_record_size 0x%zx\n", cl_data, ioe_record_size); cl_fill_ioe_records(cl_data); } -- To view, visit https://review.coreboot.org/c/coreboot/+/75910?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb5498e702497bfbc2b4d5396d5b760a0010f5de Gerrit-Change-Number: 75910 Gerrit-PatchSet: 9 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: soc/intel/meteorlake: Add support for crashlog
by Martin L Roth (Code Review) 26 Jun '23

26 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74769?usp=email ) Change subject: soc/intel/meteorlake: Add support for crashlog ...................................................................... soc/intel/meteorlake: Add support for crashlog Capture crashlog records from CPU PUNIT SRAM, SOC PMC SRAM and, IOE SRAM. Crashlog records for IOE SRAM is discovered by parsing SOC PMC SRAM records. BUG=b:262501347 TEST=Able to trigger Crashlog, BERT table gets generated and decodes as expected. Change-Id: Ib0abd697fba35edf1c03d2a3a325b7785b985cd5 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74769 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/meteorlake/Makefile.inc A src/soc/intel/meteorlake/crashlog.c A src/soc/intel/meteorlake/include/soc/crashlog.h M src/soc/intel/meteorlake/include/soc/pci_devs.h 4 files changed, 524 insertions(+), 0 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/meteorlake/Makefile.inc b/src/soc/intel/meteorlake/Makefile.inc index fd94cda..aa82381 100644 --- a/src/soc/intel/meteorlake/Makefile.inc +++ b/src/soc/intel/meteorlake/Makefile.inc @@ -31,6 +31,7 @@ ramstage-y += acpi.c ramstage-y += chip.c ramstage-y += cpu.c +ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c ramstage-y += elog.c ramstage-y += espi.c ramstage-y += finalize.c diff --git a/src/soc/intel/meteorlake/crashlog.c b/src/soc/intel/meteorlake/crashlog.c new file mode 100644 index 0000000..2e3c97a --- /dev/null +++ b/src/soc/intel/meteorlake/crashlog.c @@ -0,0 +1,498 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/bert_storage.h> +#include <console/console.h> +#include <device/pci_ops.h> +#include <intelblocks/crashlog.h> +#include <intelblocks/pmc_ipc.h> +#include <soc/crashlog.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <string.h> + +/* global crashLog info */ +static bool m_pmc_crashLog_support; +static bool m_pmc_crashLog_present; +static bool m_cpu_crashLog_support; +static bool m_cpu_crashLog_present; +static bool m_ioe_crashLog_support; +static bool m_ioe_crashLog_present; +static u32 m_pmc_crashLog_size; +static u32 m_ioe_crashLog_size; +static u32 m_cpu_crashLog_size; +static u32 cpu_crash_version; +static pmc_ipc_discovery_buf_t discovery_buf; +static pmc_crashlog_desc_table_t descriptor_table; +static tel_crashlog_devsc_cap_t cpu_cl_devsc_cap; +static cpu_crashlog_discovery_table_t cpu_cl_disc_tab; + +u32 __weak cl_get_cpu_mb_int_addr(void) +{ + return CRASHLOG_MAILBOX_INTF_ADDRESS; +} + +/* Get the SRAM BAR. */ +static uintptr_t get_sram_bar(pci_devfn_t sram_devfn) +{ + uintptr_t sram_bar; + const struct device *dev; + struct resource *res; + + dev = pcidev_path_on_root(sram_devfn); + if (!dev) { + printk(BIOS_ERR, "device: 0x%x not found!\n", sram_devfn); + return 0; + } + + res = probe_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) { + printk(BIOS_ERR, "SOC SRAM device not found!\n"); + return 0; + } + + /* Get the base address of the resource */ + sram_bar = res->base; + + return sram_bar; +} + +static void configure_sram(const struct device *sram_dev, u32 base_addr) +{ + pci_update_config16(sram_dev, PCI_COMMAND, ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY), 0); + + /* Program BAR 0 and enable command register memory space decoding */ + pci_write_config32(sram_dev, PCI_BASE_ADDRESS_0, base_addr); + pci_or_config16(sram_dev, PCI_COMMAND, PCI_COMMAND_MEMORY); +} + +void cl_get_pmc_sram_data(void) +{ + u32 *soc_pmc_dest = NULL, *ioe_pmc_dest = NULL; + u32 pmc_sram_base = cl_get_cpu_tmp_bar(); + u32 ioe_sram_base = get_sram_bar(PCI_DEVFN_IOE_SRAM); + u32 pmc_crashLog_size = cl_get_pmc_record_size(); + u32 ioe_crashLog_size = 0; + + if (!pmc_sram_base) { + printk(BIOS_ERR, "PMC SRAM base not valid\n"); + return; + } + + if (!pmc_crashLog_size) { + printk(BIOS_ERR, "No PMC crashlog records\n"); + return; + } + + if (!ioe_sram_base) { + printk(BIOS_ERR, "IOE SRAM base not valid\n"); + return; + } + + configure_sram(PCI_DEV_IOE_SRAM, ioe_sram_base); + + if (!cl_pmc_sram_has_mmio_access()) + return; + + if (!cl_ioe_sram_has_mmio_access()) + return; + + printk(BIOS_DEBUG, "PMC crashLog size : 0x%x\n", pmc_crashLog_size); + + /* allocate memory for the PMC crash records to be copied */ + unsigned long pmc_cl_cbmem_addr; + + pmc_cl_cbmem_addr = (unsigned long) cbmem_add(CBMEM_ID_PMC_CRASHLOG, + pmc_crashLog_size); + if (!pmc_cl_cbmem_addr) { + printk(BIOS_ERR, "Unable to allocate CBMEM PMC crashLog entry.\n"); + return; + } + + memset((void *)pmc_cl_cbmem_addr, 0, pmc_crashLog_size); + soc_pmc_dest = (u32 *)(uintptr_t) pmc_cl_cbmem_addr; + + bool pmc_sram = true; + + /* process crashlog records for SOC PMC SRAM */ + for (int i = 0; i < descriptor_table.numb_regions + 1; i++) { + printk(BIOS_DEBUG, "Region[0x%x].Tag=0x%x offset=0x%x, size=0x%x\n", + i, + descriptor_table.regions[i].bits.assign_tag, + descriptor_table.regions[i].bits.offset, + descriptor_table.regions[i].bits.size); + + if (!descriptor_table.regions[i].bits.size) + continue; + + if (descriptor_table.regions[i].bits.assign_tag == + CRASHLOG_DESCRIPTOR_TABLE_TAG_SOC) { + + if (cl_copy_data_from_sram(pmc_sram_base, + descriptor_table.regions[i].bits.offset, + descriptor_table.regions[i].bits.size, + soc_pmc_dest, + i, + pmc_sram)) { + soc_pmc_dest = (u32 *)((u32)soc_pmc_dest + + (descriptor_table.regions[i].bits.size + * sizeof(u32))); + } else { + pmc_crashLog_size -= descriptor_table.regions[i].bits.size * + sizeof(u32); + printk(BIOS_DEBUG, "PMC crashlog size adjusted to: 0x%x\n", + pmc_crashLog_size); + } + } else if (descriptor_table.regions[i].bits.assign_tag == + CRASHLOG_DESCRIPTOR_TABLE_TAG_IOE) { + /* + * SOC PMC crashlog records contains information about IOE SRAM + * records as well. Calculate IOE records size while parsing SOC + * PME SRAM. + */ + ioe_crashLog_size += descriptor_table.regions[i].bits.size * sizeof(u32); + } + } + + pmc_crashLog_size -= ioe_crashLog_size; + update_new_pmc_crashlog_size(&pmc_crashLog_size); + + if (ioe_crashLog_size) + m_ioe_crashLog_present = true; + else + goto pmc_send_re_arm_after_reset; + + /* allocate memory for the IOE crashlog records to be copied */ + unsigned long ioe_cl_cbmem_addr; + + ioe_cl_cbmem_addr = (unsigned long) cbmem_add(CBMEM_ID_IOE_CRASHLOG, + ioe_crashLog_size); + if (!ioe_cl_cbmem_addr) { + printk(BIOS_ERR, "Unable to allocate CBMEM IOE crashLog entry.\n"); + return; + } + + memset((void *)ioe_cl_cbmem_addr, 0, ioe_crashLog_size); + ioe_pmc_dest = (u32 *)(uintptr_t) ioe_cl_cbmem_addr; + + /* process crashlog records for IOE SRAM */ + for (int i = 0; i < descriptor_table.numb_regions + 1; i++) { + printk(BIOS_DEBUG, "Region[0x%x].Tag=0x%x offset=0x%x, size=0x%x\n", + i, + descriptor_table.regions[i].bits.assign_tag, + descriptor_table.regions[i].bits.offset, + descriptor_table.regions[i].bits.size); + + if (!descriptor_table.regions[i].bits.size) + continue; + + if (descriptor_table.regions[i].bits.assign_tag == + CRASHLOG_DESCRIPTOR_TABLE_TAG_IOE) { + + if (cl_copy_data_from_sram(ioe_sram_base, + descriptor_table.regions[i].bits.offset, + descriptor_table.regions[i].bits.size, + ioe_pmc_dest, + i, + pmc_sram)) { + ioe_pmc_dest = (u32 *)((u32)ioe_pmc_dest + + (descriptor_table.regions[i].bits.size + * sizeof(u32))); + } else { + + ioe_crashLog_size -= descriptor_table.regions[i].bits.size * + sizeof(u32); + printk(BIOS_DEBUG, "IOE crashlog size adjusted to: 0x%x\n", + ioe_crashLog_size); + } + } + } + + update_new_ioe_crashlog_size(&ioe_crashLog_size); + +pmc_send_re_arm_after_reset: + /* when bit 7 of discov cmd resp is set -> bit 2 of size field */ + cl_pmc_re_arm_after_reset(); + + /* Clear the SSRAM region after copying the error log */ + cl_pmc_clear(); +} + +bool pmc_cl_discovery(void) +{ + u32 bar_addr = 0, desc_table_addr = 0; + + const struct pmc_ipc_buffer req = { 0 }; + struct pmc_ipc_buffer res; + uint32_t cmd_reg; + int r; + + cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_CRASHLOG, + PMC_IPC_CMD_ID_CRASHLOG_DISCOVERY, + PMC_IPC_CMD_SIZE_SHIFT); + printk(BIOS_DEBUG, "cmd_reg from pmc_make_ipc_cmd %d in %s\n", cmd_reg, __func__); + + r = pmc_send_ipc_cmd(cmd_reg, &req, &res); + + if (r < 0) { + printk(BIOS_ERR, "pmc_send_ipc_cmd failed in %s\n", __func__); + return false; + } + discovery_buf.conv_val_64_bits = ((u64)res.buf[1] << 32) | res.buf[0]; + + if ((discovery_buf.conv_bits64.supported != 1) || + (discovery_buf.conv_bits64.discov_mechanism == 0) || + (discovery_buf.conv_bits64.crash_dis_sts == 1)) { + printk(BIOS_INFO, "PCH crashlog feature not supported.\n"); + m_pmc_crashLog_support = false; + m_ioe_crashLog_support = false; + m_pmc_crashLog_size = 0; + m_ioe_crashLog_size = 0; + printk(BIOS_DEBUG, "discovery_buf supported: %d, mechanism: %d, CrashDisSts: %d\n", + discovery_buf.conv_bits64.supported, + discovery_buf.conv_bits64.discov_mechanism, + discovery_buf.conv_bits64.crash_dis_sts); + return false; + } + + printk(BIOS_INFO, "PMC crashlog feature is supported.\n"); + m_pmc_crashLog_support = true; + + /* Program BAR 0 and enable command register memory space decoding */ + bar_addr = get_sram_bar(PCI_DEVFN_SRAM); + if (bar_addr == 0) { + printk(BIOS_ERR, "PCH SRAM not available, crashlog feature can't be enabled.\n"); + return false; + } + + configure_sram(PCI_DEV_SRAM, bar_addr); + + desc_table_addr = bar_addr + discovery_buf.conv_bits64.desc_tabl_offset; + m_pmc_crashLog_size = pmc_cl_gen_descriptor_table(desc_table_addr, + &descriptor_table); + printk(BIOS_DEBUG, "PMC CrashLog size in discovery mode: 0x%X\n", + m_pmc_crashLog_size); + m_pmc_crashLog_present = m_pmc_crashLog_size > 0; + + return true; +} + +u32 cl_get_cpu_bar_addr(void) +{ + u32 base_addr = 0; + if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR0) { + base_addr = pci_read_config32(PCI_DEV_TELEMETRY, PCI_BASE_ADDRESS_0) & + ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + } else if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR1) { + base_addr = pci_read_config32(PCI_DEV_TELEMETRY, PCI_BASE_ADDRESS_1) & + ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + } else { + printk(BIOS_ERR, "Invalid TEL_CFG_BAR value %d, discovery failure expected.\n", + cpu_cl_devsc_cap.discovery_data.fields.t_bir_q); + } + + return base_addr; +} + +u32 cl_get_cpu_tmp_bar(void) +{ + return get_sram_bar(PCI_DEVFN_SRAM); +} + +bool cl_pmc_sram_has_mmio_access(void) +{ + if (pci_read_config16(PCI_DEV_SRAM, PCI_VENDOR_ID) == 0xFFFF) { + printk(BIOS_ERR, "PMC SSRAM PCI device disabled. Can be enabled in device tree.\n"); + return false; + } + + return true; +} + +bool cl_ioe_sram_has_mmio_access(void) +{ + if (pci_read_config16(PCI_DEV_IOE_SRAM, PCI_VENDOR_ID) == 0xFFFF) { + printk(BIOS_ERR, "IOE SSRAM PCI device disabled. Can be enabled in device tree.\n"); + return false; + } + return true; +} + +static bool cpu_cl_get_capability(tel_crashlog_devsc_cap_t *cl_devsc_cap) +{ + cl_devsc_cap->cap_data.data = pci_read_config32(PCI_DEV_TELEMETRY, + TEL_DVSEC_OFFSET + TEL_DVSEC_PCIE_CAP_ID); + if (cl_devsc_cap->cap_data.fields.pcie_cap_id != TELEMETRY_EXTENDED_CAP_ID) { + printk(BIOS_DEBUG, "Read ID for Telemetry: 0x%x differs from expected: 0x%x\n", + cl_devsc_cap->cap_data.fields.pcie_cap_id, TELEMETRY_EXTENDED_CAP_ID); + return false; + } + + /* walk through the entries until crashLog entry */ + cl_devsc_cap->devsc_data.data_32[1] = pci_read_config32(PCI_DEV_TELEMETRY, TEL_DVSEV_ID); + int new_offset = 0; + while (cl_devsc_cap->devsc_data.fields.devsc_id != CRASHLOG_DVSEC_ID) { + if (cl_devsc_cap->cap_data.fields.next_cap_offset == 0 + || cl_devsc_cap->cap_data.fields.next_cap_offset == 0xFFFF) { + printk(BIOS_DEBUG, "Read invalid pcie_cap_id value: 0x%x\n", + cl_devsc_cap->cap_data.fields.pcie_cap_id); + return false; + } + new_offset = cl_devsc_cap->cap_data.fields.next_cap_offset; + cl_devsc_cap->cap_data.data = pci_read_config32(PCI_DEV_TELEMETRY, + new_offset + TEL_DVSEC_PCIE_CAP_ID); + cl_devsc_cap->devsc_data.data_32[1] = pci_read_config32(PCI_DEV_TELEMETRY, + new_offset + TEL_DVSEV_ID); + } + cpu_crash_version = cl_devsc_cap->devsc_data.fields.devsc_ver; + + cl_devsc_cap->discovery_data.data = pci_read_config32(PCI_DEV_TELEMETRY, new_offset + + TEL_DVSEV_DISCOVERY_TABLE_OFFSET); + + return true; +} + +static bool cpu_cl_gen_discovery_table(void) +{ + u32 bar_addr = 0, disc_tab_addr = 0; + bar_addr = cl_get_cpu_bar_addr(); + + if (!bar_addr) + return false; + + disc_tab_addr = bar_addr + + cpu_cl_devsc_cap.discovery_data.fields.discovery_table_offset; + memset(&cpu_cl_disc_tab, 0, sizeof(cpu_crashlog_discovery_table_t)); + + printk(BIOS_DEBUG, "cpu discovery table offset: 0x%x\n", + cpu_cl_devsc_cap.discovery_data.fields.discovery_table_offset); + + cpu_cl_disc_tab.header.data = ((u64)read32((u32 *)disc_tab_addr) + + ((u64)read32((u32 *)(disc_tab_addr + 4)) << 32)); + + printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer count: 0x%x\n", + cpu_cl_disc_tab.header.fields.count); + + int cur_offset = 0; + for (int i = 0; i < cpu_cl_disc_tab.header.fields.count; i++) { + cur_offset = 8 + 24*i; + cpu_cl_disc_tab.buffers[i].data = ((u64)read32((u32 *)(disc_tab_addr + + cur_offset)) + ((u64)read32((u32 *) + (disc_tab_addr + cur_offset + 4)) << 32)); + printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer: 0x%x size: " + "0x%x offset: 0x%x\n", i, cpu_cl_disc_tab.buffers[i].fields.size, + cpu_cl_disc_tab.buffers[i].fields.offset); + m_cpu_crashLog_size += cpu_cl_disc_tab.buffers[i].fields.size * sizeof(u32); + } + + if (m_cpu_crashLog_size > 0) + m_cpu_crashLog_present = true; + else + m_cpu_crashLog_present = false; + + return true; +} + +bool cpu_cl_discovery(void) +{ + memset(&cpu_cl_devsc_cap, 0, sizeof(tel_crashlog_devsc_cap_t)); + + if (!cpu_cl_get_capability(&cpu_cl_devsc_cap)) { + printk(BIOS_ERR, "CPU crashlog capability not found.\n"); + m_cpu_crashLog_support = false; + return false; + } + + m_cpu_crashLog_support = true; + + if (!cpu_cl_gen_discovery_table()) { + printk(BIOS_ERR, "CPU crashlog discovery table not valid.\n"); + m_cpu_crashLog_present = false; + return false; + } + + return true; +} + +void reset_discovery_buffers(void) +{ + memset(&discovery_buf, 0, sizeof(pmc_ipc_discovery_buf_t)); + memset(&descriptor_table, 0, sizeof(pmc_crashlog_desc_table_t)); + memset(&cpu_cl_devsc_cap, 0, sizeof(tel_crashlog_devsc_cap_t)); +} + +int cl_get_total_data_size(void) +{ + printk(BIOS_DEBUG, "crashlog size:pmc-0x%x, ioe-pmc-0x%x cpu-0x%x\n", + m_pmc_crashLog_size, m_ioe_crashLog_size, m_cpu_crashLog_size); + return m_pmc_crashLog_size + m_cpu_crashLog_size + m_ioe_crashLog_size; +} + +pmc_ipc_discovery_buf_t cl_get_pmc_discovery_buf(void) +{ + return discovery_buf; +} + +pmc_crashlog_desc_table_t cl_get_pmc_descriptor_table(void) +{ + return descriptor_table; +} + +int cl_get_pmc_record_size(void) +{ + return m_pmc_crashLog_size; +} + +int cl_get_cpu_record_size(void) +{ + return m_cpu_crashLog_size; +} + +int cl_get_ioe_record_size(void) +{ + return m_ioe_crashLog_size; +} + +bool cl_cpu_data_present(void) +{ + return m_cpu_crashLog_present; +} + +bool cl_pmc_data_present(void) +{ + return m_pmc_crashLog_present; +} + +bool cl_ioe_data_present(void) +{ + return m_ioe_crashLog_present; +} + +bool cpu_crashlog_support(void) +{ + return m_cpu_crashLog_support; +} + +bool pmc_crashlog_support(void) +{ + return m_pmc_crashLog_support; +} + +void update_new_pmc_crashlog_size(u32 *pmc_crash_size) +{ + m_pmc_crashLog_size = *pmc_crash_size; +} + +void update_new_ioe_crashlog_size(u32 *ioe_crash_size) +{ + m_ioe_crashLog_size = *ioe_crash_size; +} + +cpu_crashlog_discovery_table_t cl_get_cpu_discovery_table(void) +{ + return cpu_cl_disc_tab; +} + +void update_new_cpu_crashlog_size(u32 *cpu_crash_size) +{ + m_cpu_crashLog_size = *cpu_crash_size; +} diff --git a/src/soc/intel/meteorlake/include/soc/crashlog.h b/src/soc/intel/meteorlake/include/soc/crashlog.h new file mode 100644 index 0000000..841492d --- /dev/null +++ b/src/soc/intel/meteorlake/include/soc/crashlog.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_METEORLAKE_CRASHLOG_H_ +#define _SOC_METEORLAKE_CRASHLOG_H_ + +#include <types.h> + +/* DVSEC capability Registers */ +#define TEL_DVSEC_OFFSET 0x100 +#define TEL_DVSEC_PCIE_CAP_ID 0x0 +#define TEL_DVSEV_ID 0x8 +#define TEL_DVSEV_DISCOVERY_TABLE_OFFSET 0xC +#define TELEMETRY_EXTENDED_CAP_ID 0x23 +#define CRASHLOG_DVSEC_ID 0x04 +#define TEL_DVSEC_TBIR_BAR0 0 +#define TEL_DVSEC_TBIR_BAR1 1 + +/* CPU CrashLog MMIO Registers */ +#define CRASHLOG_MAILBOX_INTF_ADDRESS 0x6038 + +#endif /* _SOC_METEORLAKE_CRASHLOG_H_ */ diff --git a/src/soc/intel/meteorlake/include/soc/pci_devs.h b/src/soc/intel/meteorlake/include/soc/pci_devs.h index 1c4e9b2..10d8bde 100644 --- a/src/soc/intel/meteorlake/include/soc/pci_devs.h +++ b/src/soc/intel/meteorlake/include/soc/pci_devs.h @@ -60,6 +60,10 @@ #define PCI_DEVFN_GNA _PCI_DEVFN(GNA, 0) #define PCI_DEV_GNA _PCI_DEV(GNA, 0) +#define PCI_DEV_SLOT_TELEMETRY 0x0a +#define PCI_DEVFN_TELEMETRY _PCI_DEVFN(TELEMETRY, 0) +#define PCI_DEV_TELEMETRY _PCI_DEV(TELEMETRY, 0) + #define PCI_DEV_SLOT_TCSS 0x0d #define NUM_TCSS_DMA_FUNCTIONS 2 #define PCI_DEVFN_TCSS_DMA(x) _PCI_DEVFN(TCSS, ((x) + 2)) -- To view, visit https://review.coreboot.org/c/coreboot/+/74769?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0abd697fba35edf1c03d2a3a325b7785b985cd5 Gerrit-Change-Number: 74769 Gerrit-PatchSet: 29 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XL] Change in coreboot[master]: util/cbfstool: Add zstd support
by Wonkyu Kim (Code Review) 26 Jun '23

26 Jun '23

Attention is currently required from: Arthur Heymans, Julius Werner, Martin L Roth, Shelley Chen. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69753?usp=email ) Change subject: util/cbfstool: Add zstd support ...................................................................... Patch Set 3: (1 comment) File src/commonlib/zstd-1.5.2/lib/common/mem.h: https://review.coreboot.org/c/coreboot/+/69753/comment/9390c124_cf9cc7f8 : PS1, Line 174: return one.c[0]; > Hi, […] |That's not really a fair comparison (because if we found that ZSTD is a lot better |than LZMA we could drop LZMA instead) Agreed. As there is no addtional code change, LZMA code is added by default and it's because we still have file which use LZMA. I think ZSTD can be replaced for LZMA with some more optimization for not for LZ4 due to compression speed. |Also, can you clarify which compression level you used in ZSTD? (Did you play with |compression levels at all? Does it affect decompression speed?) As I don't change code, it's default compression level in the patch. |(BTW I don't really understand your FSP results. Are you saying that ZSTD |compression ratio is lower than LZ4 for that file? Are you sure that's not a |measurement error? The compression ratios are also very low compared to the |ramstage... I wonder if the reason for that—if those numbers are accurate—is that |a large part of the FSP is either already compressed or encrypted, and LZ4 is just |able to skip incompressible data with less overhead.) For FSPs result show lower rate than ramstage but not lower than LZ4. FSPs LZ4 ZSTD Raw size 204800 208896 compresed size 194449 193414 Compression ratio 5.05% 7.41% -- To view, visit https://review.coreboot.org/c/coreboot/+/69753?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34508268f8767008ef25cb9e466d201345881232 Gerrit-Change-Number: 69753 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 26 Jun 2023 17:36:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/rex: Enable Bluetooth offload for soundwire audio
by Jakub Czapiga (Code Review) 26 Jun '23

26 Jun '23

Attention is currently required from: Kapil Porwal, Tarun Tuli, Uday Bhat. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75924?usp=email ) Change subject: mb/google/rex: Enable Bluetooth offload for soundwire audio ...................................................................... Patch Set 9: (2 comments) File src/mainboard/google/rex/variants/rex0/variant.c: https://review.coreboot.org/c/coreboot/+/75924/comment/3df90c3e_e82bcc62 : PS9, Line 31: ) Missing closing bracket. https://review.coreboot.org/c/coreboot/+/75924/comment/be7cc45e_244a88a6 : PS9, Line 32: ) Missing closing bracket. -- To view, visit https://review.coreboot.org/c/coreboot/+/75924?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99df78787d9f54c91bcedf6f70352890a715cdb3 Gerrit-Change-Number: 75924 Gerrit-PatchSet: 9 Gerrit-Owner: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Comment-Date: Mon, 26 Jun 2023 17:35:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Print crashlog size info in hex
by Kapil Porwal (Code Review) 26 Jun '23

26 Jun '23

Attention is currently required from: Eric Lai, Pratikkumar V Prajapati, Subrata Banik, Tarun Tuli. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75910?usp=email ) Change subject: soc/intel/common: Print crashlog size info in hex ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75910?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb5498e702497bfbc2b4d5396d5b760a0010f5de Gerrit-Change-Number: 75910 Gerrit-PatchSet: 8 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Mon, 26 Jun 2023 16:56:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/nissa/var/gothrax: Add GPIO table for gothrax
by Derek Huang (Code Review) 26 Jun '23

26 Jun '23

Attention is currently required from: Eric Lai, Felix Singer, Henry Sun, Kangheui Won, Reka Norman, Simon Yang, Tarun Tuli, Yunlong Jia. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75872?usp=email ) Change subject: mb/google/nissa/var/gothrax: Add GPIO table for gothrax ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75872?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If852c7a30edb9fb778872414cb15dc3446aebc55 Gerrit-Change-Number: 75872 Gerrit-PatchSet: 7 Gerrit-Owner: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 26 Jun 2023 16:29:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/meteorlake: Add support for crashlog
by Subrata Banik (Code Review) 26 Jun '23

26 Jun '23

Attention is currently required from: Eric Lai, Jakub Czapiga, Kane Chen, Kapil Porwal, Paul Menzel, Pratikkumar V Prajapati, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74769?usp=email ) Change subject: soc/intel/meteorlake: Add support for crashlog ...................................................................... Patch Set 28: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74769?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0abd697fba35edf1c03d2a3a325b7785b985cd5 Gerrit-Change-Number: 74769 Gerrit-PatchSet: 28 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Mon, 26 Jun 2023 15:46:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Set system_configuration to 3 to avo...
by Martin Roth (Code Review) 26 Jun '23

26 Jun '23

Attention is currently required from: Jason Glenesk, Jason Glenesk, Jason Nien, Matt DeVillier, Tim Van Patten. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76096?usp=email ) Change subject: mb/google/skyrim/var/winterhold: Set system_configuration to 3 to avoid SMU call ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76096?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib12c73f95030625b52e26f86e932ee2aaa6ea522 Gerrit-Change-Number: 76096 Gerrit-PatchSet: 3 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Mon, 26 Jun 2023 15:43:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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