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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76117?usp=email )
Change subject: soc/amd/common/block/acpi/ivrs: fix missing IOAPIC[1] error
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/common/block/acpi/ivrs.c:
https://review.coreboot.org/c/coreboot/+/76117/comment/6d544f34_ddcdaf29 :
PS1, Line 184: dev
i think the problem is that dev is the domain device and not D0F0 on the first bus of the domain where the resource is on, so res will be NULL above
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Change subject: soc/amd/acpi/ivrs: Use specific IOMMU resource index on all SOC
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/common/block/acpi/ivrs.c:
https://review.coreboot.org/c/coreboot/+/75710/comment/4fef0370_28a1bae9 :
PS2, Line 209: } else if (dev->link_list->secondary == 0) {
: current = _acpi_fill_ivrs_ioapic(current, (u8 *)GNB_IO_APIC_ADDR,
: PCI_DEVFN(0, 1), 0);
> pushed a partial revert: CB:76117 […]
updated that one which is now the proper fix
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Hello Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/76117?usp=email
to look at the new patch set (#2).
Change subject: soc/amd/common/block/acpi/ivrs: fix missing IOAPIC[1] error
......................................................................
soc/amd/common/block/acpi/ivrs: fix missing IOAPIC[1] error
When probing the resource with the IOMMU_IOAPIC_IDX index, we need to
use the PCI device 0 function 0 on the first bus in the domain for
probing and not the domain device, since the resource isn't on the
domain device, but on the northbridge device which is B0F0D0 in the case
of the APUs.
TEST=This fixes the following error on Mandolin with Picasso:
AMD-Vi: [Firmware Bug]: : IOAPIC[1] not in IVRS table
AMD-Vi: Disabling interrupt remapping
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Id88f17d68ba5accef6561837478828bd3d24baa5
---
M src/soc/amd/common/block/acpi/ivrs.c
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/76117/2
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69783?usp=email )
Change subject: smm: Invalid the smm handler region instead of the whole
......................................................................
Patch Set 5:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69783/comment/8915d39d_d9dd3a43 :
PS5, Line 7: smm:
soc/amd: smm:
https://review.coreboot.org/c/coreboot/+/69783/comment/ce8a92fa_4268f723 :
PS5, Line 7: Invalid the smm handler region instead of the whole
Maybe:
> Invalidate SMM handler region instead of whole region
Is whole *region* correct?
https://review.coreboot.org/c/coreboot/+/69783/comment/964fc080_73b8399f :
PS5, Line 10: are
is
https://review.coreboot.org/c/coreboot/+/69783/comment/45fcc690_6d04c416 :
PS5, Line 10: will be lost
is lost
https://review.coreboot.org/c/coreboot/+/69783/comment/5a44a058_9a45897f :
PS5, Line 11: will fail
fails
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Change subject: soc/amd/acpi/ivrs: Use specific IOMMU resource index on all SOC
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/common/block/acpi/ivrs.c:
https://review.coreboot.org/c/coreboot/+/75710/comment/b683df0f_1498787d :
PS2, Line 209: } else if (dev->link_list->secondary == 0) {
: current = _acpi_fill_ivrs_ioapic(current, (u8 *)GNB_IO_APIC_ADDR,
: PCI_DEVFN(0, 1), 0);
> removing this breaks the ivrs support on mandolin/picasso: […]
pushed a partial revert: CB:76117
not sure if you want to first submit the partial revert and then fix the code or not submit the partial revert and directly fix the bug
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76117?usp=email )
Change subject: soc/amd/common/block/acpi/ivrs: fix missing IOAPIC[1] error
......................................................................
soc/amd/common/block/acpi/ivrs: fix missing IOAPIC[1] error
This isn't the proper fix, but a workaround to avoid this error:
AMD-Vi: [Firmware Bug]: : IOAPIC[1] not in IVRS table
AMD-Vi: Disabling interrupt remapping
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Id88f17d68ba5accef6561837478828bd3d24baa5
---
M src/soc/amd/common/block/acpi/ivrs.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/76117/1
diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c
index 089b42d..0160a48 100644
--- a/src/soc/amd/common/block/acpi/ivrs.c
+++ b/src/soc/amd/common/block/acpi/ivrs.c
@@ -186,6 +186,9 @@
/* Describe IOAPIC associated with the IOMMU */
current = acpi_fill_ivrs_ioapic(current, (u8 *)(uintptr_t)res->base,
PCI_DEVFN(0, 1) | (dev->link_list->secondary << 8), 0);
+ } else if (dev->link_list->secondary == 0) {
+ current = acpi_fill_ivrs_ioapic(current, (u8 *)GNB_IO_APIC_ADDR,
+ PCI_DEVFN(0, 1), 0);
}
/* If the domain has secondary bus as zero then associate HPET & FCH IOAPIC */
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Change subject: mb/{cfl,cml,whl}: Use true/false macros for s0ix_enable dt option
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75960/comment/ac23712e_d76106dc :
PS5, Line 2: lilacious
Would it be possible to use your full namee Yuchen He?
$ git config --global user.name "Yuchen He"
$ git commit --amend --author="Yuchen He <yuchenhe126(a)gmail.com>" -s
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Change subject: soc/amd/acpi/ivrs: Use specific IOMMU resource index on all SOC
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/common/block/acpi/ivrs.c:
https://review.coreboot.org/c/coreboot/+/75710/comment/6a3fcbb0_b7bb8383 :
PS2, Line 209: } else if (dev->link_list->secondary == 0) {
: current = _acpi_fill_ivrs_ioapic(current, (u8 *)GNB_IO_APIC_ADDR,
: PCI_DEVFN(0, 1), 0);
removing this breaks the ivrs support on mandolin/picasso:
AMD-Vi: [Firmware Bug]: : IOAPIC[1] not in IVRS table
AMD-Vi: Disabling interrupt remapping
putting these lines back in place and removing the leading underscore from _acpi_fill_ivrs_ioapic makes it work correctly again.
i think the problem here is that dev is the domain device and not D0F0 on the first bus of the domain where the resource is on, so res will be NULL above
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Change subject: mb/google/rex/var/rex0: Change touch over spi interrupt trigger to edge
......................................................................
Patch Set 2: Code-Review+2
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Hello Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun Tuli,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/76116?usp=email
to look at the new patch set (#2).
Change subject: mb/google/rex/var/rex0: Change touch over spi interrupt trigger to edge
......................................................................
mb/google/rex/var/rex0: Change touch over spi interrupt trigger to edge
This CL corrects the trigger for HID over SPI interrupt from Level
to Edge.
BUG:None
TEST:Touch team tested on Rex
Signed-off-by: Eran Mitrani <mitrani(a)google.com>
Change-Id: I78937af22df22d80a702477b6790a7aa40d782a4
---
M src/mainboard/google/rex/variants/rex0/include/variant/acpi/hid_spi_elan.asl
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/76116/2
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