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Change subject: mb/google/rex/var/baseboard/rex: Set TCC to 90°C
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/76110/comment/8e4c0736_7e51b1c4 :
PS1, Line 39: Tj max
I hope `Tj Max` is 110C ?
worth highlighting here in comment section ?
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Change subject: mb/google/rex/var/baseboard/rex: Set TCC to 90°C
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Patch Set 1:
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Commit Message:
https://review.coreboot.org/c/coreboot/+/76110/comment/6e28bb98_ef4eae29 :
PS1, Line 7: Set TCC to 90°C
> in ADL (Brya) we set TCC to 90°C. […]
Acknowledged
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Change subject: mb/google/dedede/var/dibbi: Update power limits
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Patch Set 10: Code-Review+2
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Change subject: mb/google/rex/var/baseboard/rex: Set TCC to 90°C
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76110/comment/46921faf_c64fdff6 :
PS1, Line 7: Set TCC to 90°C
> do you know what was the TCC value in ADL ?
in ADL (Brya) we set TCC to 90°C.
Customers can fine tune this value based on their design and test results on closed chassis system if required.
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Change subject: mb/google/rex/var/baseboard/rex: Set TCC to 90°C
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Patch Set 1:
(1 comment)
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https://review.coreboot.org/c/coreboot/+/76110/comment/f02901c8_ce315518 :
PS1, Line 7: Set TCC to 90°C
do you know what was the TCC value in ADL ?
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Change subject: mb/google/rex/var/baseboard/rex: Set TCC to 90°C
......................................................................
mb/google/rex/var/baseboard/rex: Set TCC to 90°C
Set tcc_offset value to 20 in devicetree for Thermal Control
Circuit (TCC) activation feature for rex variants.
BUG=b:270664854
BRANCH=None
TEST=Build FW and test on rex board
Change-Id: I0567b6240fcb53f38158c381b700169475cf3795
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
---
M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/76110/1
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
index 5297ce2..05e549c 100644
--- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
+++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
@@ -36,6 +36,9 @@
# DPTF enable
register "dptf_enable" = "1"
+ # Temporary setting TCC of 90C = Tj max - Tcc
+ register "tcc_offset" = "20"
+
# Enable CNVi BT
register "cnvi_bt_core" = "true"
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Change subject: mb/google/dedede: Support variant specific power limits
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Change subject: util/docker/coreboot-sdk: Do system update before installing packages
......................................................................
Patch Set 3:
(1 comment)
File util/docker/coreboot-sdk/Dockerfile:
https://review.coreboot.org/c/coreboot/+/76081/comment/6866967d_60f7e072 :
PS2, Line 20: upgrade
> People on the internet suggest to run upgrade before dist-upgrade, which seems to work most. […]
man apt-get :)
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Change subject: mb/google/nissa/var/pujjo: Tune SX9324 register for pujjoteen5
......................................................................
Patch Set 7:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75900/comment/35bc5227_60f8c5ad :
PS4, Line 7: Tuning
> Imperative mood: Tune
Done
https://review.coreboot.org/c/coreboot/+/75900/comment/274eb91a_cb8b1487 :
PS4, Line 10: P-sensor vendor
> Who is that?
The vendor is SEMTECH
https://review.coreboot.org/c/coreboot/+/75900/comment/74f94028_de0b5552 :
PS4, Line 13: TEST=i2cdump -y -f 13 0x28 on Pujjoteen5
> What is the output?
Check i2c dump register settings on Pujjoteen5
https://review.coreboot.org/c/coreboot/+/75900/comment/861353ac_2c8c8c54 :
PS4, Line 14:
> What user visible change is visible?
The P sensor function can work
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