coreboot-gerrit May 2023

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[M] Change in coreboot[master]: util/amdfwtool: Consolidate entry line regex pattern
by Raul Rangel (Code Review) 03 May '23

03 May '23

Attention is currently required from: Bao Zheng, Martin Roth, Tim Van Patten, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74950 ) Change subject: util/amdfwtool: Consolidate entry line regex pattern ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Can you verify the SHAs? -- To view, visit https://review.coreboot.org/c/coreboot/+/74950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7289ddbbec4d5daefe64f59b687ba3a4af46d052 Gerrit-Change-Number: 74950 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 03 May 2023 19:09:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: payloads/edk2: Hook up PCIe Resizable BARs flag
by Benjamin Doron (Code Review) 03 May '23

03 May '23

Attention is currently required from: Martin L Roth, Stefan Reinauer, Lean Sheng Tan. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74926 ) Change subject: payloads/edk2: Hook up PCIe Resizable BARs flag ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Ack EDK2 has resizable BARs since around 2018, from memory. It's also code that I can't remember seeing patched downstream, so it should be very safe to do for all edk2 builds. Though it might interact with the PCI library in UefiPayload, I don't think so? And that doesn't get patched much either. -- To view, visit https://review.coreboot.org/c/coreboot/+/74926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cc12d32c5e132b9f99ec650377d7683377c2a9c Gerrit-Change-Number: 74926 Gerrit-PatchSet: 2 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 03 May 2023 18:18:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/poppy/variant/nami - Move FPMCU IO setup back to ramstage
by Tarun Tuli (Code Review) 03 May '23

03 May '23

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74695 to look at the new patch set (#4). Change subject: mb/google/poppy/variant/nami - Move FPMCU IO setup back to ramstage ...................................................................... mb/google/poppy/variant/nami - Move FPMCU IO setup back to ramstage variant_board_sku() is missing depend-ices in order to work correctly in romstage. Rather than more intrusive rework as its use is limited, move the FPMCU early GPIO init back to ramstage. We still meet sufficient power off time to fully power cycle the MCU. BUG=b:245954151 TEST=Confirmed FPMCU is still functional on Nami and FP tests all pass Signed-off-by: Tarun Tuli <taruntuli(a)google.com> Change-Id: Ia428ec5aec1a0438e91bc48903bda043046b740e --- M src/mainboard/google/poppy/variants/nami/gpio.c 1 file changed, 19 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/74695/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia428ec5aec1a0438e91bc48903bda043046b740e Gerrit-Change-Number: 74695 Gerrit-PatchSet: 4 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: [DO NOT SUBMIT] use Hermes to test CFR code
by Angel Pons (Code Review) 03 May '23

03 May '23

Attention is currently required from: Patrick Rudolph, Christian Walter. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74951 ) Change subject: [DO NOT SUBMIT] use Hermes to test CFR code ...................................................................... Patch Set 1: Code-Review-2 (1 comment) Patchset: PS1: This is basically a copy-paste of the Atlas code that has been monkey-patched to build. Testing the CFR generation locally on the Hermes is more convenient. -- To view, visit https://review.coreboot.org/c/coreboot/+/74951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60327235794a4b6615a737f0b4a46a3337f0ddaa Gerrit-Change-Number: 74951 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Comment-Date: Wed, 03 May 2023 18:11:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya: Implement touchscreen power sequencing
by Matt DeVillier (Code Review) 03 May '23

03 May '23

Attention is currently required from: Tarun Tuli, Eran Mitrani. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74928 ) Change subject: mb/google/brya: Implement touchscreen power sequencing ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > (didn't mean to resolve yet) SGTM. This is the same implementation now used across most ChromeOS boards, so just need to ensure all variants are getting the GPIOs set correctly for both romstage (enabled, held in reset) and ramstage (enabled, reset released). -- To view, visit https://review.coreboot.org/c/coreboot/+/74928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e56ac4834ce69de18bef2d34f5c361a7fda1aab Gerrit-Change-Number: 74928 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Comment-Date: Wed, 03 May 2023 18:04:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/poppy/variant/nami - Move early FPMCU IO setup
by Tarun Tuli (Code Review) 03 May '23

03 May '23

Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74695 ) Change subject: mb/google/poppy/variant/nami - Move early FPMCU IO setup ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/74695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia428ec5aec1a0438e91bc48903bda043046b740e Gerrit-Change-Number: 74695 Gerrit-PatchSet: 3 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 03 May 2023 18:01:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: [DO NOT SUBMIT] use Hermes to test CFR code
by build bot (Jenkins) (Code Review) 03 May '23

03 May '23

Attention is currently required from: Patrick Rudolph, Christian Walter. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74951 ) Change subject: [DO NOT SUBMIT] use Hermes to test CFR code ...................................................................... Patch Set 1: (1 comment) File src/drivers/option/cfr.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175462): https://review.coreboot.org/c/coreboot/+/74951/comment/847363ba_bdb472d7 PS1, Line 228: printk(BIOS_DEBUG, "static __attribute__((aligned(4))) uint8_t cfr_raw_data[] = {"); Prefer __aligned(4) over __attribute__((aligned(4))) -- To view, visit https://review.coreboot.org/c/coreboot/+/74951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60327235794a4b6615a737f0b4a46a3337f0ddaa Gerrit-Change-Number: 74951 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Comment-Date: Wed, 03 May 2023 17:58:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: [WIP] mb/prodrive/atlas: Put options in CFR cbtable
by Angel Pons (Code Review) 03 May '23

03 May '23

Attention is currently required from: Sean Rhodes, Benjamin Doron, Christian Walter, Maximilian Brune, Lean Sheng Tan. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74122 ) Change subject: [WIP] mb/prodrive/atlas: Put options in CFR cbtable ...................................................................... Patch Set 4: (3 comments) File src/mainboard/prodrive/atlas/cfr.c: https://review.coreboot.org/c/coreboot/+/74122/comment/7030c91b_2d4979df PS4, Line 233: SM_DECLARE_NUMBER(profile), : SM_DECLARE_COMMENT(bad_profile), > swap these two Done https://review.coreboot.org/c/coreboot/+/74122/comment/8792f794_83a1f91d PS4, Line 247: SM_DECLARE_BOOL(pcie_sris), > missing terminator. let's be explicit about array lengths instead... Done https://review.coreboot.org/c/coreboot/+/74122/comment/b796641f_2eb533bf PS4, Line 257: SM_DECLARE_FORM(main_form), > missing terminator Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47585a9a6f94ab5005f2ab63a0df267c0caef231 Gerrit-Change-Number: 74122 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 03 May 2023 17:58:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: [DO NOT SUBMIT] use Hermes to test CFR code
by Angel Pons (Code Review) 03 May '23

03 May '23

Attention is currently required from: Patrick Rudolph, Christian Walter. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74951 ) Change subject: [DO NOT SUBMIT] use Hermes to test CFR code ...................................................................... [DO NOT SUBMIT] use Hermes to test CFR code Change-Id: I60327235794a4b6615a737f0b4a46a3337f0ddaa Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/drivers/option/cfr.c M src/mainboard/prodrive/hermes/Kconfig M src/mainboard/prodrive/hermes/Makefile.inc A src/mainboard/prodrive/hermes/cfr.c 4 files changed, 287 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/74951/1 diff --git a/src/drivers/option/cfr.c b/src/drivers/option/cfr.c index dd3ea32..b8c5c9a 100644 --- a/src/drivers/option/cfr.c +++ b/src/drivers/option/cfr.c @@ -223,4 +223,14 @@ printk(BIOS_DEBUG, "CFR: Written %u bytes of CFR structures at %p, with CRC32 0x%08x\n", menu->size, menu, menu->checksum); + + /* Dump the data as a C array for debugging */ + printk(BIOS_DEBUG, "static __attribute__((aligned(4))) uint8_t cfr_raw_data[] = {"); + for (size_t i = 0; i < menu->size; i++) { + if ((i % 16) == 0) { + printk(BIOS_DEBUG, "\n\t"); + } + printk(BIOS_DEBUG, "0x%02x, ", ((uint8_t *)menu)[i]); + } + printk(BIOS_DEBUG, "};\n"); } diff --git a/src/mainboard/prodrive/hermes/Kconfig b/src/mainboard/prodrive/hermes/Kconfig index e4ccd2d..d73cd3f 100644 --- a/src/mainboard/prodrive/hermes/Kconfig +++ b/src/mainboard/prodrive/hermes/Kconfig @@ -20,6 +20,9 @@ if BOARD_PRODRIVE_HERMES_BASEBOARD +config DRIVERS_OPTION_CFR + default y + config HERMES_USES_SPS_FIRMWARE bool "Build for use with SPS (Server Platform Services) firmware" help diff --git a/src/mainboard/prodrive/hermes/Makefile.inc b/src/mainboard/prodrive/hermes/Makefile.inc index 63be66c..0bea5db 100644 --- a/src/mainboard/prodrive/hermes/Makefile.inc +++ b/src/mainboard/prodrive/hermes/Makefile.inc @@ -5,6 +5,7 @@ romstage-y += eeprom.c +ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c ramstage-y += gpio.c ramstage-y += ramstage.c ramstage-y += mainboard.c diff --git a/src/mainboard/prodrive/hermes/cfr.c b/src/mainboard/prodrive/hermes/cfr.c new file mode 100644 index 0000000..3717618 --- /dev/null +++ b/src/mainboard/prodrive/hermes/cfr.c @@ -0,0 +1,263 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boot/coreboot_tables.h> +#include <commonlib/coreboot_tables.h> +#include <drivers/option/cfr.h> +#include <intelblocks/pmclib.h> +#include <inttypes.h> +#include <string.h> +#include <types.h> + +/* TODO: This may need to be global, or removed if auto-generating the data */ +static uint32_t atlas_get_object_id(void) +{ + static uint32_t object_id = 0; + + /* Let's start at 1: this way, option ID being 0 indicates someone messed up */ + return ++object_id; +} + +/* + * TODO: Writing this by hand is extremely tedious. Introducing a DSL + * (Domain-Specific Language) to describe options which is translated + * into code at build time may be the way to go. Maybe expand SCONFIG + * so that these can be devicetree options? + */ +void lb_board(struct lb_header *header) +{ + const bool rt_perf = false; + const bool pf_ok = true; + + const struct sm_obj_varchar serial_number = { + .object_id = atlas_get_object_id(), + .flags = CFR_OPTFLAG_READONLY | CFR_OPTFLAG_VOLATILE, + .opt_name = "serial_number", + .ui_name = "Serial Number", + .default_value = "serialnumber", + }; + + const struct sm_obj_varchar part_number = { + .object_id = atlas_get_object_id(), + .flags = CFR_OPTFLAG_READONLY | CFR_OPTFLAG_VOLATILE, + .opt_name = "part_number", + .ui_name = "Part Number", + .default_value = "partnumber", + }; + + const struct sm_obj_comment bad_profile = { + .object_id = atlas_get_object_id(), + .flags = CFR_OPTFLAG_READONLY | (pf_ok ? CFR_OPTFLAG_SUPPRESS : 0), + .ui_name = "WARNING: Profile code is invalid", + }; + + const struct sm_obj_number profile = { + .object_id = atlas_get_object_id(), + .flags = CFR_OPTFLAG_READONLY | CFR_OPTFLAG_VOLATILE, + .opt_name = "profile", + .ui_name = "Profile code", + .ui_helptext = "The profile code obtained from the EEPROM", + .default_value = 42, + }; + + const struct sm_enum_value pwr_after_g3_values[] = { + { "Power off (S5)", MAINBOARD_POWER_STATE_OFF }, + { "Power on (S0)", MAINBOARD_POWER_STATE_ON }, + /* No support for previous/last power state */ + SM_ENUM_VALUE_END, + }; + const struct sm_obj_enum power_on_after_fail = { + .object_id = atlas_get_object_id(), + .opt_name = "power_on_after_fail", + .ui_name = "Restore AC Power Loss", + .ui_helptext = "Specify what to do when power is re-applied " + "after a power loss. This option has no effect " + "on systems without a RTC battery.", + .default_value = CONFIG(POWER_STATE_OFF_AFTER_FAILURE) ? + MAINBOARD_POWER_STATE_OFF : + MAINBOARD_POWER_STATE_ON, + .values = pwr_after_g3_values, + }; + + const struct sm_enum_value primary_display_values[] = { + { "Intel iGPU", 0 }, + { "CPU PEG dGPU", 1 }, + { "PCH PCIe dGPU", 2 }, + { "Auto", 3 }, + SM_ENUM_VALUE_END, + }; + const struct sm_obj_enum primary_display = { + .object_id = atlas_get_object_id(), + .opt_name = "primary_display", + .ui_name = "Primary display device", + .ui_helptext = "Specify which display device to use as primary.", + .default_value = CONFIG(ONBOARD_VGA_IS_PRIMARY) ? 0 : 3, + .values = primary_display_values, + }; + + const struct sm_enum_value pkg_c_state_limit_values[] = { + { "C0/C1", 0 }, + { "C2", 1 }, + { "C3", 2 }, + { "C6", 3 }, + { "C7", 4 }, + { "C7S", 5 }, + { "C8", 6 }, + { "C9", 7 }, + { "C10", 8 }, + { "Default", 254 }, + { "Auto", 255 }, + SM_ENUM_VALUE_END, + }; + const struct sm_obj_enum pkg_c_state_limit = { + .object_id = atlas_get_object_id(), + .flags = rt_perf ? CFR_OPTFLAG_SUPPRESS : 0, + .opt_name = "pkg_c_state_limit", + .ui_name = "Package C-state limit", + .ui_helptext = "", /* TODO: write something */ + .default_value = rt_perf ? 0 : 255, + .values = pkg_c_state_limit_values, + }; + +#define NUM_PCIE_SSC_SETTINGS 20 + struct sm_enum_value pch_pm_pcie_pll_ssc_values[] = { + [NUM_PCIE_SSC_SETTINGS] = { "Auto", 0xff }, + SM_ENUM_VALUE_END, + }; + for (size_t i = 0; i < NUM_PCIE_SSC_SETTINGS; i++) { + char buffer[16]; + snprintf(buffer, sizeof(buffer), "%u.%u%%", i / 10, i % 10); + pch_pm_pcie_pll_ssc_values[i].ui_name = strdup(buffer); + pch_pm_pcie_pll_ssc_values[i].value = i; + } + const struct sm_obj_enum pch_pcie_pll_ssc = { + .object_id = atlas_get_object_id(), + .opt_name = "pch_pcie_pll_ssc", + .ui_name = "PCH PCIe PLL Spread Spectrum Clocking", + /* No help text */ + .default_value = 0xff, + .values = pch_pm_pcie_pll_ssc_values, + }; + + const struct sm_obj_bool c_states = { + .object_id = atlas_get_object_id(), + .flags = rt_perf ? CFR_OPTFLAG_SUPPRESS : 0, + .opt_name = "c_states", + .ui_name = "CPU power states (C-states)", + .ui_helptext = "Specify whether C-states are supported.", + .default_value = rt_perf ? false : true, + }; + + const struct sm_obj_bool hyper_threading = { + .object_id = atlas_get_object_id(), + .flags = rt_perf ? CFR_OPTFLAG_SUPPRESS : 0, + .opt_name = "hyper_threading", + .ui_name = "Hyper-Threading Technology", + /* No help text */ + .default_value = rt_perf ? false : true, + }; + + const struct sm_obj_bool turbo_mode = { + .object_id = atlas_get_object_id(), + .opt_name = "turbo_mode", + .ui_name = "Turbo Boost", + /* No help text */ + .default_value = true, + }; + + const struct sm_obj_bool energy_eff_turbo = { + .object_id = atlas_get_object_id(), + .flags = rt_perf ? CFR_OPTFLAG_SUPPRESS : 0, + .opt_name = "energy_eff_turbo", + .ui_name = "Energy Efficient Turbo", + /* No help text */ + .default_value = false, + }; + + const struct sm_obj_bool vmx = { + .object_id = atlas_get_object_id(), + .opt_name = "vmx", + .ui_name = "Intel Virtualization Technology (VT-x)", + /* No help text */ + .default_value = false, + }; + + const struct sm_obj_bool vtd = { + .object_id = atlas_get_object_id(), + .opt_name = "vtd", + .ui_name = "Intel Virtualization Technology for Directed I/O (VT-d)", + /* No help text */ + .default_value = false, + }; + + const struct sm_obj_bool ibecc = { + .object_id = atlas_get_object_id(), + .opt_name = "ibecc", + .ui_name = "In-Band ECC", + .ui_helptext = "Specify whether In-Band error checking and " + "correction is to be enabled. Enabling this " + "option will reduce the amount of available " + "RAM because some memory is needed to store " + "ECC codes.", + .default_value = false, + }; + + const struct sm_obj_bool llc_dead_line = { + .object_id = atlas_get_object_id(), + .opt_name = "llc_dead_line", + .ui_name = "LLC Dead Line Allocation", + .ui_helptext = "", /* TODO: figure out */ + .default_value = false, + }; + + const struct sm_obj_bool pcie_sris = { + .object_id = atlas_get_object_id(), + .opt_name = "pcie_sris", + .ui_name = "PCIe Separate Reference Clock with Independent SSC", + .ui_helptext = "", /* TODO: figure out */ + .default_value = false, + }; + +/* TODO: Move to cfr.h or refactor to avoid this */ +#define SM_DECLARE_ENUM(structure) { .kind = SM_OBJ_ENUM, .sm_enum = structure } +#define SM_DECLARE_NUMBER(structure) { .kind = SM_OBJ_NUMBER, .sm_number = structure } +#define SM_DECLARE_BOOL(structure) { .kind = SM_OBJ_BOOL, .sm_bool = structure } +#define SM_DECLARE_VARCHAR(structure) { .kind = SM_OBJ_VARCHAR, .sm_varchar = structure } +#define SM_DECLARE_COMMENT(structure) { .kind = SM_OBJ_COMMENT, .sm_comment = structure } +#define SM_DECLARE_FORM(structure) { .kind = SM_OBJ_FORM, .sm_form = structure } + + const struct sm_object main_contents[] = { + SM_DECLARE_VARCHAR(serial_number), + SM_DECLARE_VARCHAR(part_number), + SM_DECLARE_COMMENT(bad_profile), + SM_DECLARE_NUMBER(profile), + SM_DECLARE_ENUM(power_on_after_fail), + SM_DECLARE_ENUM(primary_display), + SM_DECLARE_ENUM(pkg_c_state_limit), + SM_DECLARE_ENUM(pch_pcie_pll_ssc), + SM_DECLARE_BOOL(c_states), + SM_DECLARE_BOOL(hyper_threading), + SM_DECLARE_BOOL(turbo_mode), + SM_DECLARE_BOOL(energy_eff_turbo), + SM_DECLARE_BOOL(vmx), + SM_DECLARE_BOOL(vtd), + SM_DECLARE_BOOL(ibecc), + SM_DECLARE_BOOL(llc_dead_line), + SM_DECLARE_BOOL(pcie_sris), + }; + + const struct sm_obj_form root_contents[] = { + { + .object_id = atlas_get_object_id(), + .ui_name = "Main", + .obj_list = main_contents, + .num_objects = ARRAY_SIZE(main_contents), + }, + }; + + const struct setup_menu_root sm_root = { + .form_list = root_contents, + .num_forms = ARRAY_SIZE(root_contents), + }; + + cfr_write_setup_menu(header, &sm_root); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/74951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60327235794a4b6615a737f0b4a46a3337f0ddaa Gerrit-Change-Number: 74951 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: [WIP] mb/prodrive/atlas: Put options in CFR cbtable
by Angel Pons (Code Review) 03 May '23

03 May '23

Attention is currently required from: Sean Rhodes, Benjamin Doron, Christian Walter, Maximilian Brune, Lean Sheng Tan. Hello build bot (Jenkins), Benjamin Doron, Christian Walter, Maximilian Brune, Lean Sheng Tan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74122 to look at the new patch set (#5). Change subject: [WIP] mb/prodrive/atlas: Put options in CFR cbtable ...................................................................... [WIP] mb/prodrive/atlas: Put options in CFR cbtable Open questions: - What to do with payload-specific options? The payload needs to know about them anyway, so describing them in coreboot kind of defeats the purpose of avoiding duplication. In our case, we can handle the profile values in the payload, which coreboot can send through CFR. - Hook up options using the option API - Figure out the details for some options (e.g. LLC dead line alloc) - Figure out if any options are missing, and if the defaults are OK The plan is to avoid having to specify the options in both edk2 and coreboot. Change-Id: I47585a9a6f94ab5005f2ab63a0df267c0caef231 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/prodrive/atlas/Kconfig M src/mainboard/prodrive/atlas/Makefile.inc A src/mainboard/prodrive/atlas/cfr.c 3 files changed, 295 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/74122/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/74122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47585a9a6f94ab5005f2ab63a0df267c0caef231 Gerrit-Change-Number: 74122 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2023