coreboot-gerrit May 2023

coreboot-gerrit@coreboot.org

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5262 discussions

[S] Change in coreboot[master]: payloads/edk2: Hook up PCIe Resizable BARs flag
by Lean Sheng Tan (Code Review) 03 May '23

03 May '23

Attention is currently required from: Martin L Roth, Matt DeVillier, Stefan Reinauer. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74926 ) Change subject: payloads/edk2: Hook up PCIe Resizable BARs flag ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > as long as it's in edk2-stable202302 I guess - or we need to make it conditional on using the upstre […] The code is generic enough, i think it should work. We only found this issue because it hangs with one of our customers with resizable bar enabled and with a big graphic card, so I dont think I can reproduce it on our side as I dont have the hardware setup. This is actually found by Benjamin, that edk2payload should also have the resizable bar flag enabled or else there might be something wrong with the resources allocation. -- To view, visit https://review.coreboot.org/c/coreboot/+/74926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cc12d32c5e132b9f99ec650377d7683377c2a9c Gerrit-Change-Number: 74926 Gerrit-PatchSet: 2 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Wed, 03 May 2023 16:27:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: payloads/edk2: Hook up PCIe Resizable BARs flag
by Matt DeVillier (Code Review) 03 May '23

03 May '23

Attention is currently required from: Martin L Roth, Stefan Reinauer, Lean Sheng Tan. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74926 ) Change subject: payloads/edk2: Hook up PCIe Resizable BARs flag ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Yes, but not with your chromebox code base though. […] as long as it's in edk2-stable202302 I guess - or we need to make it conditional on using the upstream repo -- To view, visit https://review.coreboot.org/c/coreboot/+/74926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cc12d32c5e132b9f99ec650377d7683377c2a9c Gerrit-Change-Number: 74926 Gerrit-PatchSet: 2 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 03 May 2023 16:24:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: payloads/edk2: Hook up PCIe Resizable BARs flag
by Lean Sheng Tan (Code Review) 03 May '23

03 May '23

Attention is currently required from: Martin L Roth, Matt DeVillier, Stefan Reinauer. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74926 ) Change subject: payloads/edk2: Hook up PCIe Resizable BARs flag ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > tested on any specific board? Yes, but not with your chromebox code base though. Does that still counts? -- To view, visit https://review.coreboot.org/c/coreboot/+/74926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cc12d32c5e132b9f99ec650377d7683377c2a9c Gerrit-Change-Number: 74926 Gerrit-PatchSet: 2 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Wed, 03 May 2023 16:19:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: drop custom lpc_set_resources
by Matt DeVillier (Code Review) 03 May '23

03 May '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74848 ) Change subject: soc/amd/common/block/lpc/lpc: drop custom lpc_set_resources ...................................................................... soc/amd/common/block/lpc/lpc: drop custom lpc_set_resources Drop the custom lpc_set_resources implementation that does some register access that has no effect and then calls pci_dev_set_resources and use pci_dev_set_resources for set_resources in amd_lpc_ops instead. The SPI controller's base address got configured early in boot in the lpc_set_spibase call and the enable bits got set early in boot in the lpc_enable_spi_rom call. TEST=The contents of the SPI_BASE_ADDRESS_REGISTER at the beginning and at the end of the call stay the same, so it's simply a no-op. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7a5e3e00b2e38eeb3e9dae6d6c83d11ef925ce22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74848 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/common/block/lpc/lpc.c 1 file changed, 25 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 3da3266..79a1d59 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -136,21 +136,6 @@ compact_resources(dev); } -static void lpc_set_resources(struct device *dev) -{ - struct resource *res; - u32 spi_enable_bits; - - /* Special case. The SpiRomEnable and other enables should STAY set. */ - res = find_resource(dev, 2); - spi_enable_bits = pci_read_config32(dev, SPI_BASE_ADDRESS_REGISTER); - spi_enable_bits &= SPI_BASE_ALIGNMENT - 1; - pci_write_config32(dev, SPI_BASE_ADDRESS_REGISTER, - res->base | spi_enable_bits); - - pci_dev_set_resources(dev); -} - static void configure_child_lpc_windows(struct device *dev, struct device *child) { struct resource *res; @@ -329,7 +314,7 @@ struct device_operations amd_lpc_ops = { .read_resources = lpc_read_resources, - .set_resources = lpc_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = lpc_enable_resources, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = lpc_acpi_name, -- To view, visit https://review.coreboot.org/c/coreboot/+/74848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a5e3e00b2e38eeb3e9dae6d6c83d11ef925ce22 Gerrit-Change-Number: 74848 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: report HPET MMIO
by Matt DeVillier (Code Review) 03 May '23

03 May '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74847 ) Change subject: soc/amd/common/block/lpc/lpc: report HPET MMIO ...................................................................... soc/amd/common/block/lpc/lpc: report HPET MMIO Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I77471d464dddffc63bb2f005fef3a33c84ff5f5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74847 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/common/block/lpc/lpc.c 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Matt DeVillier: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 43b3791..3da3266 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/hpet.h> #include <arch/ioapic.h> #include <console/console.h> #include <device/device.h> @@ -129,6 +130,9 @@ /* FCH IOAPIC */ mmio_range(dev, 4, IO_APIC_ADDR, 4 * KiB); + /* HPET */ + mmio_range(dev, 5, HPET_BASE_ADDRESS, 4 * KiB); + compact_resources(dev); } -- To view, visit https://review.coreboot.org/c/coreboot/+/74847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77471d464dddffc63bb2f005fef3a33c84ff5f5e Gerrit-Change-Number: 74847 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: use mmio_range to report FCH IOAPIC MMIO
by Matt DeVillier (Code Review) 03 May '23

03 May '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74846 ) Change subject: soc/amd/common/block/lpc/lpc: use mmio_range to report FCH IOAPIC MMIO ...................................................................... soc/amd/common/block/lpc/lpc: use mmio_range to report FCH IOAPIC MMIO Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I813a27e392a842188dc474018f82e10309783260 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74846 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/common/block/lpc/lpc.c 1 file changed, 15 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index edc7476..43b3791 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -126,10 +126,8 @@ /* Add a memory resource for the eSPI MMIO */ mmio_range(dev, 3, SPI_BASE_ADDRESS + ESPI_OFFSET_FROM_BAR, 4 * KiB); - res = new_resource(dev, 4); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + /* FCH IOAPIC */ + mmio_range(dev, 4, IO_APIC_ADDR, 4 * KiB); compact_resources(dev); } -- To view, visit https://review.coreboot.org/c/coreboot/+/74846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I813a27e392a842188dc474018f82e10309783260 Gerrit-Change-Number: 74846 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: report eSPI MMIO
by Matt DeVillier (Code Review) 03 May '23

03 May '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74845 ) Change subject: soc/amd/common/block/lpc/lpc: report eSPI MMIO ...................................................................... soc/amd/common/block/lpc/lpc: report eSPI MMIO Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I63fb70da3e9ded6c05354f94ee69bc6dd04e58f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74845 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/common/block/lpc/lpc.c 1 file changed, 18 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Matt DeVillier: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 5b836ea..edc7476 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -123,7 +123,10 @@ /* Add a memory resource for the SPI BAR. */ mmio_range(dev, 2, SPI_BASE_ADDRESS, 4 * KiB); - res = new_resource(dev, 3); /* IOAPIC */ + /* Add a memory resource for the eSPI MMIO */ + mmio_range(dev, 3, SPI_BASE_ADDRESS + ESPI_OFFSET_FROM_BAR, 4 * KiB); + + res = new_resource(dev, 4); /* IOAPIC */ res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -- To view, visit https://review.coreboot.org/c/coreboot/+/74845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63fb70da3e9ded6c05354f94ee69bc6dd04e58f0 Gerrit-Change-Number: 74845 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: increase size of SPI BAR to 4kByte
by Matt DeVillier (Code Review) 03 May '23

03 May '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74844 ) Change subject: soc/amd/common/block/lpc/lpc: increase size of SPI BAR to 4kByte ...................................................................... soc/amd/common/block/lpc/lpc: increase size of SPI BAR to 4kByte The memory map granularity for those devices is 4kByte. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8806128bdce8988f5cd7c8fa8a342fdb01eb7f42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74844 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/common/block/lpc/lpc.c 1 file changed, 17 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Matt DeVillier: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index b8fb923..5b836ea 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -121,7 +121,7 @@ FLASH_BELOW_4GB_MAPPING_REGION_SIZE); /* Add a memory resource for the SPI BAR. */ - mmio_range(dev, 2, SPI_BASE_ADDRESS, 1 * KiB); + mmio_range(dev, 2, SPI_BASE_ADDRESS, 4 * KiB); res = new_resource(dev, 3); /* IOAPIC */ res->base = IO_APIC_ADDR; -- To view, visit https://review.coreboot.org/c/coreboot/+/74844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8806128bdce8988f5cd7c8fa8a342fdb01eb7f42 Gerrit-Change-Number: 74844 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: report mapped SPI flash as MMIO range
by Matt DeVillier (Code Review) 03 May '23

03 May '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74839 ) Change subject: soc/amd/common/block/lpc/lpc: report mapped SPI flash as MMIO range ...................................................................... soc/amd/common/block/lpc/lpc: report mapped SPI flash as MMIO range Since the 16MByte of memory-mapped SPI flash region right below the 4GB boundary is both a fixed region and isn't decoded on a device below the LPC device, but assumed to be decoded by the LPC device itself, it shouldn't be reported as a subtractive resource, but as an MMIO resource instead. TEST=On mandolin the 16MByte MMIO-mapped SPI flash now show up as a reserved region in the e820 memory map which wasn't the case before: 13. 00000000ff000000-00000000ffffffff: RESERVED The Linux kernel doesn't show any new or possibly related errors. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Change-Id: Ib52df2b2d79a1e6213c3499984a5a1e0e25c058a Reviewed-on: https://review.coreboot.org/c/coreboot/+/74839 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/common/block/lpc/lpc.c 1 file changed, 33 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Martin L Roth: Looks good to me, approved Arthur Heymans: Looks good to me, approved Eric Lai: Looks good to me, approved Matt DeVillier: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 1fbff53..b8fb923 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -117,11 +117,8 @@ IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* Only up to 16 MByte of the SPI flash can be mapped right below 4 GB */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = FLASH_BELOW_4GB_MAPPING_REGION_BASE; - res->size = FLASH_BELOW_4GB_MAPPING_REGION_SIZE; - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + mmio_range(dev, 1, FLASH_BELOW_4GB_MAPPING_REGION_BASE, + FLASH_BELOW_4GB_MAPPING_REGION_SIZE); /* Add a memory resource for the SPI BAR. */ mmio_range(dev, 2, SPI_BASE_ADDRESS, 1 * KiB); -- To view, visit https://review.coreboot.org/c/coreboot/+/74839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib52df2b2d79a1e6213c3499984a5a1e0e25c058a Gerrit-Change-Number: 74839 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/nissa/var/uldren:Fix Touch screen power sequence
by Matt DeVillier (Code Review) 03 May '23

03 May '23

Attention is currently required from: Ian Feng, Shou-Chieh Hsu. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74835 ) Change subject: mb/google/nissa/var/uldren:Fix Touch screen power sequence ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: this can probably be dropped in favor of CB:74928 + CB:74929 -- To view, visit https://review.coreboot.org/c/coreboot/+/74835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1b1ce80aa1dd8c312e3663fc50c9e9f53cc07fe Gerrit-Change-Number: 74835 Gerrit-PatchSet: 2 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Wed, 03 May 2023 16:14:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2023