coreboot-gerrit May 2023

coreboot-gerrit@coreboot.org

1 participants
5262 discussions

[M] Change in coreboot[master]: soc/intel/cse_lite: Back up PSR data during CSE FW downgrade
by Anil Kumar K (Code Review) 03 May '23

03 May '23

Attention is currently required from: Anil Kumar K, Jérémy Compostella, Paul Menzel, Sridhar Siricilla. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74577 to look at the new patch set (#35). Change subject: soc/intel/cse_lite: Back up PSR data during CSE FW downgrade ...................................................................... soc/intel/cse_lite: Back up PSR data during CSE FW downgrade During CSE FW downgrade we erase CSE data. This would result in Platform Service Record(PSR) data to be erased. To avoid losing PSR data we need to take a backup before data clear. This patch sends PSR_HECI_FW_DOWNGRADE_BACKUP HECI command to CSE, informing the CSE to backup PSR data before a data clear operation during downgrade. To track the command send status we use CMOS address location 161. BUG=b:273207144 TEST=build CB image for google/rex board and check PSR backup command is being sent during a CSE FW downgrade. Also check PSR data is not lost/erased after a downgrade using intel PSR tool. Change-Id: I135d197b5df0a20def823fe615860b5ead4391f8 Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> --- M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 125 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/74577/35 -- To view, visit https://review.coreboot.org/c/coreboot/+/74577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I135d197b5df0a20def823fe615860b5ead4391f8 Gerrit-Change-Number: 74577 Gerrit-PatchSet: 35 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: soc/intel/meteorlake: Increase pcie snoop/no-snoop latency
by Bora Guvendik (Code Review) 03 May '23

03 May '23

Attention is currently required from: Bora Guvendik, Tarun Tuli, Jérémy Compostella, Ravishankar Sarawadi, Kapil Porwal. Bora Guvendik has uploaded a new patch set (#8) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/68308 ) Change subject: soc/intel/meteorlake: Increase pcie snoop/no-snoop latency ...................................................................... soc/intel/meteorlake: Increase pcie snoop/no-snoop latency This fixes an issue where pcie was not power gating and blocked S0ix entry. Overwrite pcie max non-snoop and snoop latency tolerance values to 5242.88us for Meteor Lake. BUG=none TEST=Boot google/rex, print/check values. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Change-Id: I9dfb9edbac95d28d50653777466ea172be64f612 --- M src/soc/intel/meteorlake/Kconfig 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/68308/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/68308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dfb9edbac95d28d50653777466ea172be64f612 Gerrit-Change-Number: 68308 Gerrit-PatchSet: 8 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: soc/intel/cmn/pcie: Allow SoC to overwrite snoop/no-snoop latency
by Bora Guvendik (Code Review) 03 May '23

03 May '23

Attention is currently required from: Bora Guvendik, Hannah Williams, Subrata Banik, Jérémy Compostella, Paul Menzel. Hello build bot (Jenkins), Hannah Williams, Subrata Banik, Jérémy Compostella, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74141 to look at the new patch set (#6). Change subject: soc/intel/cmn/pcie: Allow SoC to overwrite snoop/no-snoop latency ...................................................................... soc/intel/cmn/pcie: Allow SoC to overwrite snoop/no-snoop latency In case SoC requires different pcie max non-snoop and snoop latency tolerance, let it overwrite the common code settings. BUG=none TEST=Boot google/rex and print/check if able to overwrite values. Change-Id: Ic2b9a158d219e6c6e7f6e7f0ae0f093c1183b402 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/include/device/pciexp.h M src/soc/intel/common/block/pcie/Kconfig M src/soc/intel/common/block/pcie/pcie.c 3 files changed, 30 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/74141/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/74141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2b9a158d219e6c6e7f6e7f0ae0f093c1183b402 Gerrit-Change-Number: 74141 Gerrit-PatchSet: 6 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: soc/intel/apollolake: Only use 8 bits for afterg3
by Sean Rhodes (Code Review) 03 May '23

03 May '23

Attention is currently required from: Matt DeVillier. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74955 ) Change subject: soc/intel/apollolake: Only use 8 bits for afterg3 ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/74955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb290d1480b03cb3425edc6ff29b9c78a6545df1 Gerrit-Change-Number: 74955 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Wed, 03 May 2023 20:29:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: util/amdfwtool: Consolidate entry line regex pattern
by Tim Van Patten (Code Review) 03 May '23

03 May '23

Attention is currently required from: Bao Zheng, Martin Roth, Karthik Ramasubramanian, Felix Held. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74950 ) Change subject: util/amdfwtool: Consolidate entry line regex pattern ...................................................................... Patch Set 1: (2 comments) File util/amdfwtool/data_parse.c: https://review.coreboot.org/c/coreboot/+/74950/comment/b8a4a73b_0b80116c PS1, Line 651: 3 `OPT_LEVEL` = 4 now, meaning the index has changed. Does anyone outside of this rely on these index values being stable? https://review.coreboot.org/c/coreboot/+/74950/comment/faf109d6_42377301 PS1, Line 56: OPT_SPACE1, This value is shifting `OPT_LEVEL` from `3` to `4`. It's also never used. Why is it needed? -- To view, visit https://review.coreboot.org/c/coreboot/+/74950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7289ddbbec4d5daefe64f59b687ba3a4af46d052 Gerrit-Change-Number: 74950 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 03 May 2023 19:53:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: report HPET MMIO
by 9elements QA (Code Review) 03 May '23

03 May '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74847 ) Change subject: soc/amd/common/block/lpc/lpc: report HPET MMIO ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 12 / 1 / 13 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/160962 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/160960 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/160959 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/160958 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/160957 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/160956 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/160955 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/160954 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/160953 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/160952 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/160951 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/160950 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/160949 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/74847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77471d464dddffc63bb2f005fef3a33c84ff5f5e Gerrit-Change-Number: 74847 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 03 May 2023 19:52:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/dedede: Add SOF chip driver
by Sean Rhodes (Code Review) 03 May '23

03 May '23

Attention is currently required from: Tarun Tuli, Matt DeVillier. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74818 ) Change subject: mb/google/dedede: Add SOF chip driver ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9452b11af614d8727aa8dd448e37f7a06faa450d Gerrit-Change-Number: 74818 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Wed, 03 May 2023 19:29:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/google/brya: Add SOF chip driver
by Sean Rhodes (Code Review) 03 May '23

03 May '23

Attention is currently required from: Tarun Tuli, Matt DeVillier. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74817 ) Change subject: mb/google/brya: Add SOF chip driver ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12614b85f9779cc40d83a9c868cc46b110f26af6 Gerrit-Change-Number: 74817 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Wed, 03 May 2023 19:29:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/volteer: Add SOF chip driver
by Sean Rhodes (Code Review) 03 May '23

03 May '23

Attention is currently required from: Tarun Tuli, Matt DeVillier, Nick Vaccaro. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74816 ) Change subject: mb/google/volteer: Add SOF chip driver ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62a96149cec9eeb7b2da8a2337083969a1b0fce0 Gerrit-Change-Number: 74816 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 03 May 2023 19:29:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/puff: Add SOF chip driver
by Sean Rhodes (Code Review) 03 May '23

03 May '23

Attention is currently required from: Tarun Tuli, Matt DeVillier. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74815 ) Change subject: mb/google/puff: Add SOF chip driver ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I421c070eac321c2fc160b8f26868bcb1ec13001e Gerrit-Change-Number: 74815 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Wed, 03 May 2023 19:29:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2023