coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct PCI MMIO BAR window
by build bot (Jenkins) (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Matt DeVillier. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74809 ) Change subject: soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct PCI MMIO BAR window ...................................................................... Patch Set 2: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175136): https://review.coreboot.org/c/coreboot/+/74809/comment/375854c8_a458cd94 PS2, Line 9: This ports back commit commit d75ee46d3ce6 ("soc/amd/picasso/acpi: Possible repeated word: 'commit' -- To view, visit https://review.coreboot.org/c/coreboot/+/74809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19153947cbb1b1b684291765eb1902caac65b9ec Gerrit-Change-Number: 74809 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 14:55:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct PCI MMIO BAR window
by Felix Held (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Matt DeVillier. Hello build bot (Jenkins), Matt DeVillier, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74809 to look at the new patch set (#2). Change subject: soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct PCI MMIO BAR window ...................................................................... soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct PCI MMIO BAR window This ports back commit commit d75ee46d3ce6 ("soc/amd/picasso/acpi: Change PCI0 BAR window") to Stoneyridge so that the correct end of the non-fixed MMIO region gets reported in PCI0's _CRS method. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I19153947cbb1b1b684291765eb1902caac65b9ec --- M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl 1 file changed, 16 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/74809/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19153947cbb1b1b684291765eb1902caac65b9ec Gerrit-Change-Number: 74809 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: adjust the eDP panel power sequence
by Martin L Roth (Code Review) 27 Apr '23

27 Apr '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74790 ) Change subject: mb/google/skyrim/var/winterhold: adjust the eDP panel power sequence ...................................................................... mb/google/skyrim/var/winterhold: adjust the eDP panel power sequence Set edp_panel_t9_ms to 8ms which means it will delay 8ms between backlight off and vary backlight off. BUG=b:271704149 BRANCH=Skyrim TEST=Build; Verify the UPD was passed to system integrated table; Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: I952d05b18e29cf30256f43562a5052007c5c6268 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74790 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk(a)gmail.com> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb 1 file changed, 24 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jason Glenesk: Looks good to me, approved Eric Lai: Looks good to me, approved Matt DeVillier: Looks good to me, approved Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb index 2e32b28..d8603b7 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb @@ -114,6 +114,7 @@ # The unit is set to one per ms register "edp_panel_t8_ms" = "112" + register "edp_panel_t9_ms" = "8" device ref gpp_bridge_1 on # Required so the NVMe gets placed into D3 when entering S0i3. -- To view, visit https://review.coreboot.org/c/coreboot/+/74790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I952d05b18e29cf30256f43562a5052007c5c6268 Gerrit-Change-Number: 74790 Gerrit-PatchSet: 6 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/mendocino: update FSP parameters for eDP power sequence adjus...
by Martin L Roth (Code Review) 27 Apr '23

27 Apr '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74789 ) Change subject: soc/amd/mendocino: update FSP parameters for eDP power sequence adjustment ...................................................................... soc/amd/mendocino: update FSP parameters for eDP power sequence adjustment Add UPD parameter for eDP power sequence adjustment. The edp_panel_t9_ms parameter is set for bloff to varybloff. BUG=b:271704149 BRANCH=Skyrim TEST=Build; Verify the UPD was pass to system integrated table. Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Id651c9cc4d6f4e27f6c78ca10ca12936d66ef43b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74789 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk(a)gmail.com> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/mendocino/chip.h M src/soc/amd/mendocino/fsp_m_params.c 2 files changed, 27 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jason Glenesk: Looks good to me, approved Eric Lai: Looks good to me, approved Matt DeVillier: Looks good to me, approved Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index 5eb7c41..f161038 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -179,6 +179,8 @@ /* Set for eDP power sequence adjustment timing T8 (from varybl to blon). */ uint8_t edp_panel_t8_ms; + /* Set for eDP power sequence adjustment timing T9 (from bloff to varybloff). */ + uint8_t edp_panel_t9_ms; }; diff --git a/src/soc/amd/mendocino/fsp_m_params.c b/src/soc/amd/mendocino/fsp_m_params.c index cea26a9..6582a7c 100644 --- a/src/soc/amd/mendocino/fsp_m_params.c +++ b/src/soc/amd/mendocino/fsp_m_params.c @@ -171,6 +171,7 @@ mcfg->dxio_tx_vboost_enable = config->dxio_tx_vboost_enable; mcfg->edp_panel_t8_ms = config->edp_panel_t8_ms; + mcfg->edp_panel_t9_ms = config->edp_panel_t9_ms; fsp_fill_pcie_ddi_descriptors(mcfg); fsp_assign_ioapic_upds(mcfg); -- To view, visit https://review.coreboot.org/c/coreboot/+/74789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id651c9cc4d6f4e27f6c78ca10ca12936d66ef43b Gerrit-Change-Number: 74789 Gerrit-PatchSet: 5 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: vc/amd/fsp/mendocino/FspmUpd: Add UPD to set eDP panel T9 vaule
by Martin L Roth (Code Review) 27 Apr '23

27 Apr '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74788 ) Change subject: vc/amd/fsp/mendocino/FspmUpd: Add UPD to set eDP panel T9 vaule ...................................................................... vc/amd/fsp/mendocino/FspmUpd: Add UPD to set eDP panel T9 vaule Add UPD edp_panel_t9_ms for eDP panel sequence adjustment. BUG=b:271704149 BRANCH=Skyrim Test=Build/Boot to ChromeOS Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Idc1a212e9c203584a6497fd6cbd3f995eeb030f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74788 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk(a)gmail.com> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/amd/fsp/mendocino/FspmUpd.h 1 file changed, 24 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Jason Glenesk: Looks good to me, approved Eric Lai: Looks good to me, approved Matt DeVillier: Looks good to me, approved Martin Roth: Looks good to me, approved diff --git a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h index b3d6dc3..e2622dd 100644 --- a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h +++ b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h @@ -102,7 +102,8 @@ /** Offset 0x04E5**/ uint32_t vrm_soc_current_limit_mA; /** Offset 0x04E9**/ uint8_t fch_usb_3_port_force_gen1; /** Offset 0x04EA**/ uint8_t edp_panel_t8_ms; - /** Offset 0x04EB**/ uint8_t UnusedUpdSpace2[277]; + /** Offset 0x04EB**/ uint8_t edp_panel_t9_ms; + /** Offset 0x04EC**/ uint8_t UnusedUpdSpace2[276]; /** Offset 0x0600**/ uint16_t UpdTerminator; } FSP_M_CONFIG; -- To view, visit https://review.coreboot.org/c/coreboot/+/74788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc1a212e9c203584a6497fd6cbd3f995eeb030f2 Gerrit-Change-Number: 74788 Gerrit-PatchSet: 5 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/mendocino: rename pwr_on_vary_bl_to_blon to edp_panel_t8_ms
by Martin L Roth (Code Review) 27 Apr '23

27 Apr '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74787 ) Change subject: soc/amd/mendocino: rename pwr_on_vary_bl_to_blon to edp_panel_t8_ms ...................................................................... soc/amd/mendocino: rename pwr_on_vary_bl_to_blon to edp_panel_t8_ms Rename the UPD pwr_on_vary_bl_to_blon to edp_panel_t8_ms to match the eDP sequence timing in milliseconds. BUG=b:271704149 BRANCH=Skyrim Test=Build/Boot to ChromeOS Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Iecdfe47cd9142d8a1ddeee0ec988d37b2a11028e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74787 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk(a)gmail.com> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb M src/soc/amd/mendocino/chip.h M src/soc/amd/mendocino/fsp_m_params.c M src/vendorcode/amd/fsp/mendocino/FspmUpd.h 4 files changed, 30 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Jason Glenesk: Looks good to me, approved Eric Lai: Looks good to me, approved Matt DeVillier: Looks good to me, approved Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb index 4297f90..2e32b28 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb @@ -112,8 +112,8 @@ register "dxio_tx_vboost_enable" = "1" - # The unit is set to one per 4ms - register "pwr_on_vary_bl_to_blon" = "0x1c" + # The unit is set to one per ms + register "edp_panel_t8_ms" = "112" device ref gpp_bridge_1 on # Required so the NVMe gets placed into D3 when entering S0i3. diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index 774ce5e..5eb7c41 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -177,9 +177,8 @@ /* Force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1 */ union usb3_force_gen1 usb3_port_force_gen1; - /* Set for eDP power sequence adjustment timing from varybl to blon. The unit is set to - one per 4ms*/ - uint8_t pwr_on_vary_bl_to_blon; + /* Set for eDP power sequence adjustment timing T8 (from varybl to blon). */ + uint8_t edp_panel_t8_ms; }; diff --git a/src/soc/amd/mendocino/fsp_m_params.c b/src/soc/amd/mendocino/fsp_m_params.c index 453ce69..cea26a9 100644 --- a/src/soc/amd/mendocino/fsp_m_params.c +++ b/src/soc/amd/mendocino/fsp_m_params.c @@ -170,7 +170,7 @@ } mcfg->dxio_tx_vboost_enable = config->dxio_tx_vboost_enable; - mcfg->pwr_on_vary_bl_to_blon = config->pwr_on_vary_bl_to_blon; + mcfg->edp_panel_t8_ms = config->edp_panel_t8_ms; fsp_fill_pcie_ddi_descriptors(mcfg); fsp_assign_ioapic_upds(mcfg); diff --git a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h index 391c64b..b3d6dc3 100644 --- a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h +++ b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h @@ -101,8 +101,8 @@ /** Offset 0x04E1**/ uint32_t vrm_maximum_current_limit_mA; /** Offset 0x04E5**/ uint32_t vrm_soc_current_limit_mA; /** Offset 0x04E9**/ uint8_t fch_usb_3_port_force_gen1; - /** Offset 0x04E9**/ uint8_t pwr_on_vary_bl_to_blon; - /** Offset 0x04EA**/ uint8_t UnusedUpdSpace2[277]; + /** Offset 0x04EA**/ uint8_t edp_panel_t8_ms; + /** Offset 0x04EB**/ uint8_t UnusedUpdSpace2[277]; /** Offset 0x0600**/ uint16_t UpdTerminator; } FSP_M_CONFIG; -- To view, visit https://review.coreboot.org/c/coreboot/+/74787 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecdfe47cd9142d8a1ddeee0ec988d37b2a11028e Gerrit-Change-Number: 74787 Gerrit-PatchSet: 3 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/poppy: Add support for variant SKU romstage GPIO configs
by Tarun Tuli (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Shelley Chen, Subrata Banik, Eric Lai. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73211 ) Change subject: mb/google/poppy: Add support for variant SKU romstage GPIO configs ...................................................................... Patch Set 8: (1 comment) File src/mainboard/google/poppy/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/73211/comment/f71e2df3_32b40e95 PS7, Line 392: > please drop one extra line? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/73211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I593a23951306908fadc00e6bc8d9d310f09c5e4b Gerrit-Change-Number: 73211 Gerrit-PatchSet: 8 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 14:30:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/poppy: Add support for variant SKU romstage GPIO configs
by Subrata Banik (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Shelley Chen, Tarun Tuli, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73211 ) Change subject: mb/google/poppy: Add support for variant SKU romstage GPIO configs ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/poppy/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/73211/comment/88b99a52_58f81e59 PS7, Line 392: please drop one extra line? -- To view, visit https://review.coreboot.org/c/coreboot/+/73211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I593a23951306908fadc00e6bc8d9d310f09c5e4b Gerrit-Change-Number: 73211 Gerrit-PatchSet: 7 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 14:29:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/starlabs/starbook: Select SOC_INTEL_COMMON_BLOCK_TCSS
by Lean Sheng Tan (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Sean Rhodes. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74521 ) Change subject: mb/starlabs/starbook: Select SOC_INTEL_COMMON_BLOCK_TCSS ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Is this needed? It has been selected in src/soc/intel/alderlake/Kconfig: […] is this needed? -- To view, visit https://review.coreboot.org/c/coreboot/+/74521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1515c10329ca3114141826570eab433cd076426f Gerrit-Change-Number: 74521 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Thu, 27 Apr 2023 14:28:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/starlabs/starbook: Select SOC_INTEL_COMMON_BLOCK_TCSS
by Lean Sheng Tan (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Sean Rhodes. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74521 ) Change subject: mb/starlabs/starbook: Select SOC_INTEL_COMMON_BLOCK_TCSS ...................................................................... Patch Set 1: -Code-Review (1 comment) Patchset: PS1: Is this needed? It has been selected in src/soc/intel/alderlake/Kconfig: config SOC_INTEL_ALDERLAKE_TCSS_USB4_SUPPORT bool default y if !SOC_INTEL_ALDERLAKE_PCH_S -- To view, visit https://review.coreboot.org/c/coreboot/+/74521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1515c10329ca3114141826570eab433cd076426f Gerrit-Change-Number: 74521 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Thu, 27 Apr 2023 14:27:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2023