coreboot-gerrit April 2023

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[M] Change in coreboot[master]: vc/google: Decouple DSM_CALIB from CHROMEOS
by Matt DeVillier (Code Review) 27 Apr '23

27 Apr '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74812 ) Change subject: vc/google: Decouple DSM_CALIB from CHROMEOS ...................................................................... vc/google: Decouple DSM_CALIB from CHROMEOS DSM (Dynamic Speaker Management) uses calibration parameters stored in a VPD (Vital Product Data) FMAP region to configure the audio output via an ACPI _DSD table. This has no dependency on a ChromeOS, and can be used by Linux/Windows drivers if appropriately configured. Remove the dependency of DSM_CALIB (and the calibration file) on CHROMEOS and replace it with VPD, so that non-CHROMEOS builds can utilize this feature as well. Move files from underneath vc/google/chromeos to underscore the point. TEST=build/boot google/nightfury, dump ACPI, verify DSM calibraton parameters present in _DSD table. Change-Id: I643b3581bcc662befc9e30736dae806f94b055af Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/drivers/i2c/max98390/max98390.c M src/drivers/i2c/rt1011/rt1011.c M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/hatch/Kconfig M src/mainboard/google/volteer/Kconfig M src/vendorcode/google/Kconfig M src/vendorcode/google/Makefile.inc M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/Makefile.inc M src/vendorcode/google/chromeos/chromeos.h R src/vendorcode/google/dsm_calib.c A src/vendorcode/google/dsm_calib.h 12 files changed, 82 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/74812/1 diff --git a/src/drivers/i2c/max98390/max98390.c b/src/drivers/i2c/max98390/max98390.c index 12c8c9d..ba25e1a 100644 --- a/src/drivers/i2c/max98390/max98390.c +++ b/src/drivers/i2c/max98390/max98390.c @@ -7,7 +7,7 @@ #include <device/device.h> #include <device/path.h> #include <stdint.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <vendorcode/google/dsm_calib.h> #include "chip.h" #define MAX98390_ACPI_HID "MX98390" @@ -46,7 +46,7 @@ acpigen_write_resourcetemplate_footer(); /* Device Properties */ - if (CONFIG(CHROMEOS_DSM_CALIB)) { + if (CONFIG(GOOGLE_DSM_CALIB)) { if (get_dsm_calibration_from_key(config->r0_calib_key, &r0_value) || get_dsm_calibration_from_key(config->temperature_calib_key, &temp_value)) { @@ -62,7 +62,7 @@ } } - if (CONFIG(CHROMEOS_DSM_PARAM_FILE_NAME)) { + if (CONFIG(GOOGLE_DSM_PARAM_FILE_NAME)) { if (config->dsm_param_file_name) { if (!dp) dp = acpi_dp_new_table("_DSD"); diff --git a/src/drivers/i2c/rt1011/rt1011.c b/src/drivers/i2c/rt1011/rt1011.c index 6977d95..9a21748 100644 --- a/src/drivers/i2c/rt1011/rt1011.c +++ b/src/drivers/i2c/rt1011/rt1011.c @@ -7,7 +7,7 @@ #include <device/device.h> #include <device/path.h> #include <stdint.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <vendorcode/google/dsm_calib.h> #include "chip.h" #define RT1011_ACPI_HID "10EC1011" @@ -45,7 +45,7 @@ acpigen_write_resourcetemplate_footer(); /* Device Properties */ - if (CONFIG(CHROMEOS_DSM_CALIB)) { + if (CONFIG(GOOGLE_DSM_CALIB)) { if (get_dsm_calibration_from_key(config->r0_calib_key, &r0_value) || get_dsm_calibration_from_key(config->temperature_calib_key, &temp_value)) { diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 9cdc8e7..14aa8d0 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -57,16 +57,16 @@ config BOARD_GOOGLE_GIMBLE bool "-> Gimble" select BOARD_GOOGLE_BASEBOARD_BRYA - select CHROMEOS_DSM_CALIB if CHROMEOS - select CHROMEOS_DSM_PARAM_FILE_NAME if CHROMEOS + select GOOGLE_DSM_CALIB if VPD + select GOOGLE_DSM_PARAM_FILE_NAME if VPD select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_I2C_MAX98390 config BOARD_GOOGLE_GIMBLE4ES bool "-> Gimble4ES" select BOARD_GOOGLE_BASEBOARD_BRYA - select CHROMEOS_DSM_CALIB if CHROMEOS - select CHROMEOS_DSM_PARAM_FILE_NAME if CHROMEOS + select GOOGLE_DSM_CALIB if VPD + select GOOGLE_DSM_PARAM_FILE_NAME if VPD select DEFAULT_ADL_NEM select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_I2C_MAX98390 @@ -118,8 +118,8 @@ config BOARD_GOOGLE_REDRIX bool "-> Redrix" select BOARD_GOOGLE_BASEBOARD_BRYA - select CHROMEOS_DSM_CALIB if CHROMEOS - select CHROMEOS_DSM_PARAM_FILE_NAME if CHROMEOS + select GOOGLE_DSM_CALIB if VPD + select GOOGLE_DSM_PARAM_FILE_NAME if VPD select DRIVERS_GENESYSLOGIC_GL9755 select DRIVERS_GFX_GENERIC select DRIVERS_I2C_MAX98390 @@ -130,8 +130,8 @@ config BOARD_GOOGLE_REDRIX4ES bool "-> Redrix4ES" select BOARD_GOOGLE_BASEBOARD_BRYA - select CHROMEOS_DSM_CALIB if CHROMEOS - select CHROMEOS_DSM_PARAM_FILE_NAME if CHROMEOS + select GOOGLE_DSM_CALIB if VPD + select GOOGLE_DSM_PARAM_FILE_NAME if VPD select DEFAULT_ADL_NEM select DRIVERS_GENESYSLOGIC_GL9755 select DRIVERS_GFX_GENERIC diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 3522787..d2c0ca1 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -43,13 +43,13 @@ config BOARD_GOOGLE_HELIOS select BOARD_GOOGLE_BASEBOARD_HATCH - select CHROMEOS_DSM_CALIB if CHROMEOS + select GOOGLE_DSM_CALIB if VPD select DRIVERS_I2C_RT1011 select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_HELIOS_DISKSWAP select BOARD_GOOGLE_BASEBOARD_HATCH - select CHROMEOS_DSM_CALIB if CHROMEOS + select GOOGLE_DSM_CALIB if VPD select DRIVERS_I2C_RT1011 select INTEL_GMA_HAVE_VBT @@ -73,13 +73,13 @@ config BOARD_GOOGLE_NIGHTFURY select BOARD_GOOGLE_BASEBOARD_HATCH - select CHROMEOS_DSM_CALIB if CHROMEOS + select GOOGLE_DSM_CALIB if VPD select DRIVERS_I2C_MAX98390 select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_PALKIA select BOARD_GOOGLE_BASEBOARD_HATCH - select CHROMEOS_DSM_CALIB if CHROMEOS + select GOOGLE_DSM_CALIB if VPD select DRIVERS_I2C_RT1011 if BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 51210e4..62d2fe9 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -51,7 +51,7 @@ config BOARD_GOOGLE_LINDAR select BOARD_GOOGLE_BASEBOARD_VOLTEER - select CHROMEOS_DSM_CALIB if CHROMEOS + select GOOGLE_DSM_CALIB if VPD select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_I2C_RT1011 select INTEL_CAR_NEM diff --git a/src/vendorcode/google/Kconfig b/src/vendorcode/google/Kconfig index 60c0c22..796f8b4 100644 --- a/src/vendorcode/google/Kconfig +++ b/src/vendorcode/google/Kconfig @@ -9,3 +9,22 @@ help Provide a common implementation for mainboard version, which returns a formatted 'rev%d' board_id() string. + +config GOOGLE_DSM_CALIB + bool + default n + depends on VPD + help + On some boards, there are calibrated parameters for Dynamic Speaker Management(DSM) + stored in VPD. Enable this config to read and parse these VPD values and write them + to ACPI DSD table in device driver. These parameters will be applied by kernel driver + through device property at boot. + +config GOOGLE_DSM_PARAM_FILE_NAME + bool + default n + depends on GOOGLE_DSM_CALIB + help + On some boards, there are different dsm parameter files for Dynamic Speaker + Management (DSM). Enable this config to assign dsm parameters file name in ACPI + SSDT table. Kernel driver uses this to load the DSM parameter file. diff --git a/src/vendorcode/google/Makefile.inc b/src/vendorcode/google/Makefile.inc index c67ea20..c9e8389 100644 --- a/src/vendorcode/google/Makefile.inc +++ b/src/vendorcode/google/Makefile.inc @@ -2,4 +2,5 @@ subdirs-$(CONFIG_CHROMEOS) += chromeos +ramstage-$(CONFIG_GOOGLE_DSM_CALIB) += dsm_calib.c ramstage-$(CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION) += smbios.c diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 8684920..0979652 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -57,23 +57,6 @@ help Use the AP watchdog flag stored in EC. -config CHROMEOS_DSM_CALIB - bool - default n - help - On some boards, there are calibrated parameters for Dynamic Speaker Management(DSM) - stored in VPD. Enable this config to read and parse these VPD values and write them - to ACPI DSD table in device driver. These parameters will be applied by kernel driver - through device property at boot. - -config CHROMEOS_DSM_PARAM_FILE_NAME - bool - default n - help - On some boards, there are different dsm parameter files for Dynamic Speaker - Management (DSM). Enable this config to assign dsm parameters file name in ACPI - SSDT table. Kernel driver uses this to load the DSM parameter file. - config CHROMEOS_CSE_BOARD_RESET_OVERRIDE bool default n diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index ce77194..fbfd7a4 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -8,7 +8,6 @@ ramstage-$(CONFIG_CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME) += tpm2.c ramstage-$(CONFIG_HAVE_REGULATORY_DOMAIN) += wrdd.c ramstage-$(CONFIG_USE_SAR) += sar.c -ramstage-$(CONFIG_CHROMEOS_DSM_CALIB) += dsm_calib.c ramstage-$(CONFIG_TPM_GOOGLE) += cr50_enable_update.c romstage-$(CONFIG_CHROMEOS_CSE_BOARD_RESET_OVERRIDE) += cse_board_reset.c diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 98aa4fa..cab855d 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -27,16 +27,6 @@ void chromeos_set_me_hash(u32*, int); void chromeos_set_ramoops(void *ram_oops, size_t size); -/** - * get_dsm_calibration_from_key - Gets value related to DSM calibration from VPD - * @key: The key in RO_VPD. The valid prefix is "dsm_calib_". The valid keys are - * documented in https://chromeos.google.com/partner/dlm/docs/factory/vpd.html. - * @value: Output value. The value read from VPD parsed into uint64_t integer. - * - * Returns CB_SUCCESS on success or CB_ERR on failure. - */ -enum cb_err get_dsm_calibration_from_key(const char *key, uint64_t *value); - /* * Declaration for mainboards to use to generate ACPI-specific ChromeOS needs. */ diff --git a/src/vendorcode/google/chromeos/dsm_calib.c b/src/vendorcode/google/dsm_calib.c similarity index 94% rename from src/vendorcode/google/chromeos/dsm_calib.c rename to src/vendorcode/google/dsm_calib.c index ad4291d..a245b80 100644 --- a/src/vendorcode/google/chromeos/dsm_calib.c +++ b/src/vendorcode/google/dsm_calib.c @@ -5,7 +5,7 @@ #include <stdint.h> #include <string.h> #include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include "dsm_calib.h" #define DSM_BUF_LEN 128 #define DSM_PREFIX "dsm_calib_" diff --git a/src/vendorcode/google/dsm_calib.h b/src/vendorcode/google/dsm_calib.h new file mode 100644 index 0000000..efbfe04 --- /dev/null +++ b/src/vendorcode/google/dsm_calib.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DSM_CALIB_H__ +#define __DSM_CALIB_H__ + +#include <stddef.h> +#include <stdint.h> +#include <types.h> + +/** + * get_dsm_calibration_from_key - Gets value related to DSM calibration from VPD + * @key: The key in RO_VPD. The valid prefix is "dsm_calib_". The valid keys are + * documented in https://chromeos.google.com/partner/dlm/docs/factory/vpd.html. + * @value: Output value. The value read from VPD parsed into uint64_t integer. + * + * Returns CB_SUCCESS on success or CB_ERR on failure. + */ +enum cb_err get_dsm_calibration_from_key(const char *key, uint64_t *value); + +#endif /* __DSM_CALIB_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74812 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I643b3581bcc662befc9e30736dae806f94b055af Gerrit-Change-Number: 74812 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel: Make CSE sync in romstage default disable
by Subrata Banik (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Tarun Tuli, Kapil Porwal, Sridhar Siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74805 ) Change subject: soc/intel: Make CSE sync in romstage default disable ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/cannonlake/Kconfig: https://review.coreboot.org/c/coreboot/+/74805/comment/5057344a_c94cd43e PS2, Line 115: if SOC_INTEL_CSE_LITE_SKU > When CSE Lite should happen is board choice, i don't this should part of SoC Kconfig list. moving into chromeos specific board, there would be too much effort doing such. Please feel free to pick this if you think there are better ways to do so. take a look into https://review.coreboot.org/c/coreboot/+/74805/2/src/soc/intel/cannonlake/K… there is no such hard rule that SOC_INTEL_CSE_LITE_SKU check can't exist inside SoC code. -- To view, visit https://review.coreboot.org/c/coreboot/+/74805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f5017fbcf917201eaf8233089050bd31c3d1917 Gerrit-Change-Number: 74805 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 17:08:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: [WIP] mb/prodrive/atlas: Put options in CFR cbtable
by Benjamin Doron (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Sean Rhodes, Christian Walter, Angel Pons, Maximilian Brune, Lean Sheng Tan. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74122 ) Change subject: [WIP] mb/prodrive/atlas: Put options in CFR cbtable ...................................................................... Patch Set 2: (1 comment) File src/mainboard/prodrive/atlas/cfr.c: https://review.coreboot.org/c/coreboot/+/74122/comment/945d9b57_f325f309 PS1, Line 14: struct sm_enum_value pwr_after_g3_values[] = { : { "Power on (S0)", 0 }, : { "Power off (S5)", 1 }, : SM_ENUM_VALUE_END, : }; > Done The string<->enum are still mismatched? -- To view, visit https://review.coreboot.org/c/coreboot/+/74122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47585a9a6f94ab5005f2ab63a0df267c0caef231 Gerrit-Change-Number: 74122 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 17:06:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel: Make CSE sync in romstage default disable
by Sridhar Siricilla (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74805 ) Change subject: soc/intel: Make CSE sync in romstage default disable ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/cannonlake/Kconfig: https://review.coreboot.org/c/coreboot/+/74805/comment/aff764e9_78fc6802 PS2, Line 115: if SOC_INTEL_CSE_LITE_SKU > > Hmm why this flag is required when SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE itself indicate that deals […] When CSE Lite should happen is board choice, i don't this should part of SoC Kconfig list. -- To view, visit https://review.coreboot.org/c/coreboot/+/74805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f5017fbcf917201eaf8233089050bd31c3d1917 Gerrit-Change-Number: 74805 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 16:42:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/common/block/graphics: Add missing cbfs_unmap()
by Tim Van Patten (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Konrad Adamczyk, Raul Rangel, Matt DeVillier, Paul Menzel, Grzegorz Bernacki, Fred Reitberger, Felix Held. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74779 ) Change subject: soc/amd/common/block/graphics: Add missing cbfs_unmap() ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6fbbfd36f0974551befef4d08423a8148e151e7 Gerrit-Change-Number: 74779 Gerrit-PatchSet: 2 Gerrit-Owner: Grzegorz Bernacki Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Konrad Adamczyk <konrada(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Grzegorz Bernacki Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 Apr 2023 16:38:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Select FSP MULTIPHASE SI INIT RETURN BROKEN config
by build bot (Jenkins) (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Derek Huang, Kapil Porwal. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74785 ) Change subject: soc/intel/alderlake: Select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN config ...................................................................... Patch Set 5: Verified+1 (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175139): https://review.coreboot.org/c/coreboot/+/74785/comment/411bc019_9f54b6c8 PS5, Line 6: Possible long commit subject (prefer a maximum 65 characters) -- To view, visit https://review.coreboot.org/c/coreboot/+/74785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18a918cca7e19e03ed6020c55c86c64a94212963 Gerrit-Change-Number: 74785 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 16:38:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: acpi: Add missing cbfs_unmap()
by Tim Van Patten (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Lance Zhao, Konrad Adamczyk, Tim Wawrzynczak, Grzegorz Bernacki, Karthik Ramasubramanian. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74715 ) Change subject: acpi: Add missing cbfs_unmap() ...................................................................... Patch Set 4: Code-Review+1 (1 comment) File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/74715/comment/fe6e7765_7759f7d8 PS4, Line 1954: cbfs_unmap(dsdt_file); Please add a comment indicating why this is being unmapped after `slic_file`, even though the last usage of `dsdt_file` was earlier. -- To view, visit https://review.coreboot.org/c/coreboot/+/74715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf7ba6842f42404ad8bb415f8e7fda10403cbe2e Gerrit-Change-Number: 74715 Gerrit-PatchSet: 4 Gerrit-Owner: Grzegorz Bernacki Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Konrad Adamczyk <konrada(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Grzegorz Bernacki Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 16:38:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/common: Introduce API to get the FSP Reset Status
by Subrata Banik (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Derek Huang, Paul Menzel, Kapil Porwal, Andrey Petrov. Hello build bot (Jenkins), Tarun Tuli, Derek Huang, Kapil Porwal, Arthur Heymans, Eric Lai, Andrey Petrov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74783 to look at the new patch set (#5). Change subject: soc/intel/common: Introduce API to get the FSP Reset Status ...................................................................... soc/intel/common: Introduce API to get the FSP Reset Status This patch creates a function to read the FSP API Reset Status. This function relies on the FSP Scheduled Reset HOB which holds the reset type (warm/cold/shutdown) information along with any platform specific reset need (like global reset). Ideally FSP API should be able to return the status (both success and error code) upon exiting the FSP API but unfortunately there are some scenarios in ADL/RPL FSP where MultiPhaseSiInit API is unable to return any ERROR status. Hence, this function provides an additional hook to read the FSP reset status by reading the dedicated HOB without relying on the FSP API exit status code. Additionally, create FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN config option to handle broken FSP API return status issue. Any SoC platform that selects the `FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN` config will call into this newly added API to get the FSP return status from MultiPhaseSiInit. BUG=b:278665768 TEST=Able to select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN for ADL/RPL SoC code and call into this API to know the return status from MultiPhaseSiInit FSP API. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ief5d79736cc11a0a31ca2889128285795f8b5aae --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/common/fsp_reset.c M src/soc/intel/common/reset.h 3 files changed, 126 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/74783/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/74783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief5d79736cc11a0a31ca2889128285795f8b5aae Gerrit-Change-Number: 74783 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/common: Introduce API to get the FSP Reset Status
by Subrata Banik (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Derek Huang, Paul Menzel, Kapil Porwal, Andrey Petrov. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74783 ) Change subject: soc/intel/common: Introduce API to get the FSP Reset Status ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/fsp_reset.c: https://review.coreboot.org/c/coreboot/+/74783/comment/a416117a_ecc65b91 PS3, Line 66: reset_type > > `hob->reset_type` is - […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/74783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief5d79736cc11a0a31ca2889128285795f8b5aae Gerrit-Change-Number: 74783 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 16:37:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel: Make CSE sync in romstage default disable
by Subrata Banik (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Tarun Tuli, Kapil Porwal, Sridhar Siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74805 ) Change subject: soc/intel: Make CSE sync in romstage default disable ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/cannonlake/Kconfig: https://review.coreboot.org/c/coreboot/+/74805/comment/d39a32c5_00884f79 PS2, Line 115: if SOC_INTEL_CSE_LITE_SKU > Hmm why this flag is required when SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE itself indicate that deals with CSE Lite? we avoid non-chromeos platforms failing while compiling (not meeting the kconfig dependency) > May be it(SOC_INTEL_CSE_LITE_SKU) can be added as dependent to KConfig SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE. I don't see need for this condition here. dependency is there already. -- To view, visit https://review.coreboot.org/c/coreboot/+/74805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f5017fbcf917201eaf8233089050bd31c3d1917 Gerrit-Change-Number: 74805 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 16:34:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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