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Change subject: soc/intel: Make CSE sync in romstage default disable
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/cannonlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/74805/comment/f87857ed_94cabcb3
PS2, Line 115: if SOC_INTEL_CSE_LITE_SKU
Hmm why this flag is required when SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE itself indicate that deals with CSE Lite? May be it(SOC_INTEL_CSE_LITE_SKU) can be added as dependent to KConfig SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE. I don't see need for this condition here.
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Change subject: mb/google,intel: Use common ChromeEC code for SMI APMC
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Patch Set 3:
(1 comment)
Patchset:
PS3:
> Right, I missed the added MKBP here, but noticed in CB:74603 for the chromeec_smi_sleep() case and l […]
since Matt's test didn't result in some noticeable breakage, i'll mark this one as resolved
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Change subject: [WIP] mb/google: Re-arrange mainboard_smi_sleep()
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Patch Set 1:
(1 comment)
File src/mainboard/google/auron/smihandler.c:
https://review.coreboot.org/c/coreboot/+/74604/comment/8304e290_24a51827
PS1, Line 47: case ACPI_S4:
are we sure these board properly support S4?
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Change subject: [WIP] ACPI: Add usb_charge_mode_from_gnvs()
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Patch Set 4:
(2 comments)
File src/acpi/acpi_pm.c:
https://review.coreboot.org/c/coreboot/+/74524/comment/ab568866_943f17f2
PS4, Line 69: *usb0_disable, bool *usb1_disable)
these variable names make the functionality much more clear, I'd recommend using them throughout the patch vs using u0/u1disable
File src/ec/google/chromeec/smihandler.c:
https://review.coreboot.org/c/coreboot/+/74524/comment/b237c827_956f237d
PS4, Line 48: chromeec_set_usb_charge_mode(bool u0disable, bool u1disable)
: {
: if (u0disable)
: google_chromeec_set_usb_charge_mode(0, USB_CHARGE_MODE_DISABLED);
:
: if (u1disable)
: google_chromeec_set_usb_charge_mode(1, USB_CHARGE_MODE_DISABLED);
any reason not to just pass in the sleep mode, and have chromeec_set_usb_charge_mode() get the disable state directly from usb_charge_mode_from_gnvs() ? Seem like a bit of extra work to have each board get the disable states and then pass them here
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Change subject: soc/amd: Reserve PCIe MMCONF in ACPI
......................................................................
Patch Set 2: -Code-Review
(1 comment)
Patchset:
PS2:
> i tested on both mandolin (picasso) and careena (stoneyridge). […]
hm, not sure if the change in /proc/iomem is an improvement.
on mandolin it was before
f8000000-fbffffff : PCI MMCONFIG 0000 [bus 00-3f]
f8000000-fbffffff : Reserved
and is now
f8000000-fbffffff : PCI MMCONFIG 0000 [bus 00-3f]
f8000000-fbffffff : Reserved
f8000000-fbffffff : PCI Bus 0000:00
there's also
d0000000-f7ffffff : PCI Bus 0000:00
so i'd guess that the PCI Bus means PCI MMIO and not MMCONF?!
the vendor UEFI firmware on some laptop with AMD APU returns the MMCONF region as DWordMemory from the PCI0 _CRS method; it uses DWordMemory instead of Memory32Fixed everywhere though, so DWordMemory vs Memory32Fixed likely isn't the issue
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