coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

1 participants
5761 discussions

[S] Change in coreboot[master]: soc/intel/common: Don't hardcode ramtop offset
by Sean Rhodes (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Sean Rhodes, Subrata Banik, Dinesh Gehlot, Lean Sheng Tan. Hello build bot (Jenkins), Nico Huber, Subrata Banik, Lean Sheng Tan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74511 to look at the new patch set (#10). Change subject: soc/intel/common: Don't hardcode ramtop offset ...................................................................... soc/intel/common: Don't hardcode ramtop offset The `ramtop_cmos_offset` can be obtained from the `option.h`, so remove the hardcoded value. Change-Id: I5327b5d4e78b715a85072e5d9a62cf8fd2ae92c0 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/common/basecode/ramtop/ramtop.c 1 file changed, 25 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/74511/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/74511 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5327b5d4e78b715a85072e5d9a62cf8fd2ae92c0 Gerrit-Change-Number: 74511 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: arch/x86/include/pci_io_cfg: introduce PCI_IO_CONFIG_[INDEX,DATA] define
by Felix Held (Code Review) 27 Apr '23

27 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74791 ) Change subject: arch/x86/include/pci_io_cfg: introduce PCI_IO_CONFIG_[INDEX,DATA] define ...................................................................... arch/x86/include/pci_io_cfg: introduce PCI_IO_CONFIG_[INDEX,DATA] define Instead of having multiple instances of the same magic numbers in the code, introduce and use the PCI_IO_CONFIG_INDEX and PCI_IO_CONFIG_DATA definitions. TEST=Timeless build for Mandolin results in identical image. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If6f6f058180cf36cae7921ce3c7aaf1a0c75c7b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74791 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/arch/x86/include/arch/pci_io_cfg.h 1 file changed, 37 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Sridhar Siricilla: Looks good to me, approved Fred Reitberger: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h index 5e69288..4cf8c7c 100644 --- a/src/arch/x86/include/arch/pci_io_cfg.h +++ b/src/arch/x86/include/arch/pci_io_cfg.h @@ -7,6 +7,9 @@ #include <arch/io.h> #include <device/pci_type.h> +#define PCI_IO_CONFIG_INDEX 0xcf8 +#define PCI_IO_CONFIG_DATA 0xcfc + static __always_inline uint32_t pci_io_encode_addr(pci_devfn_t dev, uint16_t reg) { @@ -25,48 +28,48 @@ uint8_t pci_io_read_config8(pci_devfn_t dev, uint16_t reg) { uint32_t addr = pci_io_encode_addr(dev, reg); - outl(addr, 0xCF8); - return inb(0xCFC + (reg & 3)); + outl(addr, PCI_IO_CONFIG_INDEX); + return inb(PCI_IO_CONFIG_DATA + (reg & 3)); } static __always_inline uint16_t pci_io_read_config16(pci_devfn_t dev, uint16_t reg) { uint32_t addr = pci_io_encode_addr(dev, reg); - outl(addr, 0xCF8); - return inw(0xCFC + (reg & 2)); + outl(addr, PCI_IO_CONFIG_INDEX); + return inw(PCI_IO_CONFIG_DATA + (reg & 2)); } static __always_inline uint32_t pci_io_read_config32(pci_devfn_t dev, uint16_t reg) { uint32_t addr = pci_io_encode_addr(dev, reg); - outl(addr, 0xCF8); - return inl(0xCFC); + outl(addr, PCI_IO_CONFIG_INDEX); + return inl(PCI_IO_CONFIG_DATA); } static __always_inline void pci_io_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value) { uint32_t addr = pci_io_encode_addr(dev, reg); - outl(addr, 0xCF8); - outb(value, 0xCFC + (reg & 3)); + outl(addr, PCI_IO_CONFIG_INDEX); + outb(value, PCI_IO_CONFIG_DATA + (reg & 3)); } static __always_inline void pci_io_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value) { uint32_t addr = pci_io_encode_addr(dev, reg); - outl(addr, 0xCF8); - outw(value, 0xCFC + (reg & 2)); + outl(addr, PCI_IO_CONFIG_INDEX); + outw(value, PCI_IO_CONFIG_DATA + (reg & 2)); } static __always_inline void pci_io_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value) { uint32_t addr = pci_io_encode_addr(dev, reg); - outl(addr, 0xCF8); - outl(value, 0xCFC); + outl(addr, PCI_IO_CONFIG_INDEX); + outl(value, PCI_IO_CONFIG_DATA); } #if !CONFIG(ECAM_MMCONF_SUPPORT) -- To view, visit https://review.coreboot.org/c/coreboot/+/74791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6f6f058180cf36cae7921ce3c7aaf1a0c75c7b9 Gerrit-Change-Number: 74791 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: configs/builder: add default config for Intel Archer City CRB
by Felix Held (Code Review) 27 Apr '23

27 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71969 ) ( 13 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: configs/builder: add default config for Intel Archer City CRB ...................................................................... configs/builder: add default config for Intel Archer City CRB which is based on Intel Sapphire Rapids Scalable Processor chipset which was product launched on Jan. 10 2023. The site-local/* files are Intel binaries that are not published yet but coreboot build validation system would skip these binaries when they are in "site-local" directory. Please make sure you have the correct Intel binaries for your AC CRB and place them to the right location accordingly. CONFIG_PAYLOAD_FILE="site-local/archercity/linuxboot_bzImage" is LinuxBoot payload, there are several ways to build it, one way is to build it from the x86_64 qemu example from osf-builder: git clone https://github.com/linuxboot/osf-builder cd examples/qemu; make kernel commit ae90fc0bb (soc/intel/xeon_sp/spr: Default to X2APIC support) would enable DEFAULT_X2APIC_RUNTIME, your LinuxBoot kernel needs to enable X2APIC support, otherwise need to set CONFIG_XAPIC_ONLY=y in your defconfig. Change-Id: I15aefc3edb2d22fc00d854850e948fe2048a992e Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71969 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Reviewed-by: Johnny Lin <Johnny_Lin(a)wiwynn.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A configs/builder/config.intel.crb.ac 1 file changed, 58 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Jonathan Zhang: Looks good to me, approved Johnny Lin: Looks good to me, approved diff --git a/configs/builder/config.intel.crb.ac b/configs/builder/config.intel.crb.ac new file mode 100644 index 0000000..d2db58d --- /dev/null +++ b/configs/builder/config.intel.crb.ac @@ -0,0 +1,23 @@ +# Intel ArcherCity CRB is a dual socket CRB based on Intel +# Sapphire Rapids Scalable Processor (SPR-SP) chipset. +# +# Type this in coreboot root directory to get a working .config: +# make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.ac + +CONFIG_VENDOR_INTEL=y +CONFIG_BOARD_INTEL_ARCHERCITY_CRB=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200" +CONFIG_PAYLOAD_LINUX=y +CONFIG_PAYLOAD_FILE="site-local/archercity/linuxboot_bzImage" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_T_FILE="site-local/archercity/Server_T.fd" +CONFIG_FSP_M_FILE="site-local/archercity/Server_M.fd" +CONFIG_FSP_S_FILE="site-local/archercity/Server_S.fd" +CONFIG_IFD_BIN_PATH="site-local/archercity/descriptor.bin" +CONFIG_ME_BIN_PATH="site-local/archercity/me.bin" +CONFIG_CPU_UCODE_BINARIES="site-local/archercity/mbf806f8.mcb" +CONFIG_VALIDATE_INTEL_DESCRIPTOR=y -- To view, visit https://review.coreboot.org/c/coreboot/+/71969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15aefc3edb2d22fc00d854850e948fe2048a992e Gerrit-Change-Number: 71969 Gerrit-PatchSet: 15 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-CC: Jian-Ming Wang <jianmingW(a)supermicro.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-CC: TimLiu-SMCI <timliu(a)supermicro.com.tw> Gerrit-CC: Ziang Wang <ziang.wang(a)intel.com> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: mb/google/poppy/variant/nami - Ensure power cycle of FPMCU on startup
by Tarun Tuli (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Paul Menzel, Eric Lai. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73212 ) Change subject: mb/google/poppy/variant/nami - Ensure power cycle of FPMCU on startup ...................................................................... Patch Set 4: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/73212/comment/fbde6697_c4ffa512 PS3, Line 7: mb/google/poppy: Nami - invoke power cycle of FPMCU on startup > Please use the common style for the variant prefix. Done https://review.coreboot.org/c/coreboot/+/73212/comment/b6858518_e74f7b7f PS3, Line 8: > Please add a problem description in the beginning. Done https://review.coreboot.org/c/coreboot/+/73212/comment/31e5c42d_134da7b1 PS3, Line 17: seconds > Remove. Done https://review.coreboot.org/c/coreboot/+/73212/comment/d1f11a1a_191ca858 PS3, Line 16: Confirmed FPMCU is still functional on Nami. : Confirmed power is off for 150ms seconds on boot. : Confirmed RCC_CSR of FPMCU indicates power cycle occurred. : Confirmed reset is de-asserted approx 3ms after power application : (target >2.5ms) > Format as list? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/73212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a23bda96bc2ea90be81a2310605f75c55c0a839 Gerrit-Change-Number: 73212 Gerrit-PatchSet: 4 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 13:38:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/google/poppy/variant/nami - Ensure power cycle of FPMCU on startup
by Tarun Tuli (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Tarun Tuli, Eric Lai. Hello Subrata Banik, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73212 to look at the new patch set (#4). Change subject: mb/google/poppy/variant/nami - Ensure power cycle of FPMCU on startup ...................................................................... mb/google/poppy/variant/nami - Ensure power cycle of FPMCU on startup Add functionality to ensure that the FPMCU is power cycled long enough on boot to ensure proper reset. This solution relies solely on coreboot to sequence the power and reset signals appropriately (150ms on boot). -Confirmed power is off for 150ms on boot. -Confirmed RCC_CSR of FPMCU indicates power cycle occurred. -Confirmed reset is de-asserted approx 3ms after power application (target >2.5ms) BUG=b:245954151 TEST=Confirmed FPMCU is still functional on Nami and timings are as expected. Change-Id: I0a23bda96bc2ea90be81a2310605f75c55c0a839 Signed-off-by: Tarun Tuli <taruntuli(a)google.com> --- M src/mainboard/google/poppy/variants/nami/gpio.c M src/mainboard/google/poppy/variants/nami/mainboard.c 2 files changed, 99 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/73212/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/73212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a23bda96bc2ea90be81a2310605f75c55c0a839 Gerrit-Change-Number: 73212 Gerrit-PatchSet: 4 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: mb/starlabs/starbook: Let coreboot configure ASPM
by Paul Menzel (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Sean Rhodes. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74520 ) Change subject: mb/starlabs/starbook: Let coreboot configure ASPM ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74520/comment/f99988d1_8be5b93c PS1, Line 10: lower power consumption How much lower? Any idea, what the reason is? -- To view, visit https://review.coreboot.org/c/coreboot/+/74520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib15eaede956f0aa55118d093fdff0fd9487df250 Gerrit-Change-Number: 74520 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Thu, 27 Apr 2023 13:21:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: [RFC] drivers/option: Add option list in cbtable
by Sean Rhodes (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Benjamin Doron, Angel Pons, Maximilian Brune, Lean Sheng Tan. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74121 ) Change subject: [RFC] drivers/option: Add option list in cbtable ...................................................................... Patch Set 3: (1 comment) File src/drivers/option/cfr.c: https://review.coreboot.org/c/coreboot/+/74121/comment/302ef74a_88d7fa42 PS3, Line 103: option->option_id = option_id; : option->flags = flags; : option->default_value = default_value; : option->size = sizeof(*option); : : current += option->size; : current += sm_write_opt_name(current, opt_name) `opt` and `option` - should be the same -- To view, visit https://review.coreboot.org/c/coreboot/+/74121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I304de7d26d79245a2e31a6d01f6c5643b31cb772 Gerrit-Change-Number: 74121 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Maslowski <info(a)orangecms.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 13:20:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/common: Adjust ramtop to work with more than just CMOS
by Sean Rhodes (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Angel Pons, Lean Sheng Tan. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74747 ) Change subject: soc/intel/common: Adjust ramtop to work with more than just CMOS ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/74747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08b6b1507f6eecd8190bf970fd324d9b48c2fe91 Gerrit-Change-Number: 74747 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 13:06:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: ec/starlabs/merlin: Change the fallback value for fn_ctrl_swap
by Sean Rhodes (Code Review) 27 Apr '23

27 Apr '23

Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74744 ) Change subject: ec/starlabs/merlin: Change the fallback value for fn_ctrl_swap ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/74744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fcbb497f14ed0c97ff05c6c01a3929522786781 Gerrit-Change-Number: 74744 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 27 Apr 2023 13:06:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/starlabs/starbook: Select SOC_INTEL_COMMON_BLOCK_TCSS
by Sean Rhodes (Code Review) 27 Apr '23

27 Apr '23

Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74521 ) Change subject: mb/starlabs/starbook: Select SOC_INTEL_COMMON_BLOCK_TCSS ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/74521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1515c10329ca3114141826570eab433cd076426f Gerrit-Change-Number: 74521 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 27 Apr 2023 13:06:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2023