coreboot-gerrit April 2023

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[XL] Change in coreboot[master]: ACPI,SMBIOS : Provide ACPI and SMBIOS support for RISC-V
by weidongwd (Code Review) 27 Apr '23

27 Apr '23

weidongwd has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/74808 ) Change subject: ACPI,SMBIOS : Provide ACPI and SMBIOS support for RISC-V ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/74808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3924c15a07960f42753b02fbfbb4df5b0a5a866 Gerrit-Change-Number: 74808 Gerrit-PatchSet: 1 Gerrit-Owner: weidongwd <weidong.wd(a)bytedance.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: soc/amd/common/block/graphics: Add missing cbfs_unmap()
by Jakub Czapiga (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Konrad Adamczyk, Raul Rangel, Matt DeVillier, Paul Menzel, Grzegorz Bernacki, Tim Van Patten, Fred Reitberger, Felix Held. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74779 ) Change subject: soc/amd/common/block/graphics: Add missing cbfs_unmap() ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74779/comment/5453cbc9_f706248d PS2, Line 13: BUG=278264488 Google bugs should use format: `BUG=b:9999` for buganizer or `BUG=chromium:9999` for public tracker. -- To view, visit https://review.coreboot.org/c/coreboot/+/74779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6fbbfd36f0974551befef4d08423a8148e151e7 Gerrit-Change-Number: 74779 Gerrit-PatchSet: 2 Gerrit-Owner: Grzegorz Bernacki Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Konrad Adamczyk <konrada(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Grzegorz Bernacki Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 Apr 2023 12:44:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: device/pci_rom: Add simple pci_rom_free()
by Jakub Czapiga (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Konrad Adamczyk, Paul Menzel, Grzegorz Bernacki, Felix Held. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74778 ) Change subject: device/pci_rom: Add simple pci_rom_free() ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74778/comment/b05366fc_491baf27 PS2, Line 14: BUG=278264488 Google bugs should use format: `BUG=b:9999` for buganizer or `BUG=chromium:9999` for public tracker. -- To view, visit https://review.coreboot.org/c/coreboot/+/74778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc9aad34b6bf101a3a0c06b92ed2dc6f2d7b9b33 Gerrit-Change-Number: 74778 Gerrit-PatchSet: 2 Gerrit-Owner: Grzegorz Bernacki Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Konrad Adamczyk <konrada(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Grzegorz Bernacki Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 Apr 2023 12:44:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: acpi: Add missing cbfs_unmap()
by Jakub Czapiga (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Lance Zhao, Konrad Adamczyk, Tim Wawrzynczak, Grzegorz Bernacki, Tim Van Patten, Karthik Ramasubramanian. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74715 ) Change subject: acpi: Add missing cbfs_unmap() ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74715/comment/41e7406b_e6664275 PS4, Line 11: : BUG=278264488 Google bugs should use format: `BUG=b:9999` for buganizer or `BUG=chromium:9999` for public tracker. -- To view, visit https://review.coreboot.org/c/coreboot/+/74715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf7ba6842f42404ad8bb415f8e7fda10403cbe2e Gerrit-Change-Number: 74715 Gerrit-PatchSet: 4 Gerrit-Owner: Grzegorz Bernacki Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Konrad Adamczyk <konrada(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Grzegorz Bernacki Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 12:43:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/common/block/cpu: Add missing cbfs_unmap()
by Jakub Czapiga (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Konrad Adamczyk, Jason Glenesk, Raul Rangel, Matt DeVillier, Paul Menzel, Grzegorz Bernacki, Arthur Heymans, Tim Van Patten, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74777 ) Change subject: soc/amd/common/block/cpu: Add missing cbfs_unmap() ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74777/comment/305b83ff_fd1d01ff PS2, Line 12: BUG=278264488 Google bugs should use format: `BUG=b:9999` for buganizer or `BUG=chromium:9999` for public tracker. File src/soc/amd/common/block/cpu/update_microcode.c: https://review.coreboot.org/c/coreboot/+/74777/comment/a05885d2_3cbf7ad8 PS2, Line 101: cbfs_unmap((void *)ucode); : ucode = NULL; : timestamp_add_now(TS_READ_UCODE_END); : return; nit: ``` timestamp_add_now(TS_READ_UCODE_END); goto end; ... if (atomic_read(&cpus_updated) >= get_cpu_count()) { end: cbfs_unmap((void *)ucode); ucode = NULL; } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/74777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I200d24df6157cc6d06bade34809faefea9f0090a Gerrit-Change-Number: 74777 Gerrit-PatchSet: 2 Gerrit-Owner: Grzegorz Bernacki Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Konrad Adamczyk <konrada(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Grzegorz Bernacki Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 Apr 2023 12:43:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct number of PCI buses
by build bot (Jenkins) (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Matt DeVillier. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74809 ) Change subject: soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct number of PCI buses ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175117): https://review.coreboot.org/c/coreboot/+/74809/comment/4aeef39e_0ec11f84 PS1, Line 9: This ports back commit commit d75ee46d3ce6 ("soc/amd/picasso/acpi: Possible repeated word: 'commit' -- To view, visit https://review.coreboot.org/c/coreboot/+/74809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19153947cbb1b1b684291765eb1902caac65b9ec Gerrit-Change-Number: 74809 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 12:35:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct number of PCI buses
by Felix Held (Code Review) 27 Apr '23

27 Apr '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74809 ) Change subject: soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct number of PCI buses ...................................................................... soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct number of PCI buses This ports back commit commit d75ee46d3ce6 ("soc/amd/picasso/acpi: Change PCI0 BAR window") to Stoneyridge so that the correct end of the non-fixed MMIO region gets reported in PCI0's _CRS method. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I19153947cbb1b1b684291765eb1902caac65b9ec --- M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl 1 file changed, 16 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/74809/1 diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index dad8aaa..a4903e9 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -98,16 +98,9 @@ CreateDWordField(CRES, ^MMIO._BAS, MM1B) CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ + /* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */ MM1B = TOM1 - Local0 = 0x10000000 << 4 + Local0 = CONFIG_ECAM_MMCONF_BASE_ADDRESS Local0 -= TOM1 MM1L = Local0 -- To view, visit https://review.coreboot.org/c/coreboot/+/74809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19153947cbb1b1b684291765eb1902caac65b9ec Gerrit-Change-Number: 74809 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[XL] Change in coreboot[master]: ACPI,SMBIOS : Provide ACPI and SMBIOS support for RISC-V
by build bot (Jenkins) (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Lance Zhao, Philipp Hug, Tim Wawrzynczak, ron minnich. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74808 ) Change subject: ACPI,SMBIOS : Provide ACPI and SMBIOS support for RISC-V ...................................................................... Patch Set 1: (96 comments) File src/acpi/acpi.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/bc278798_d2ddbffd PS1, Line 390: static void acpi_create_pptt (acpi_header_t *pptt) space prohibited between function name and open parenthesis '(' File src/arch/riscv/tables.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/14816d47_9fe23b5f PS1, Line 27: unsigned long high_table_pointer, new_high_table_pointer;; Statements terminations use 1 semicolon Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/c13da519_bd76ea95 PS1, Line 34: memset ((void *)high_table_pointer, 0, MAX_SMBIOS_SIZE); space prohibited between function name and open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/ba34c33a_a7f27a15 PS1, Line 64: memset ((void *)high_table_pointer, 0, max_acpi_size); space prohibited between function name and open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/081cde2e_8912a1be PS1, Line 88: const char *config_path[] = { "cfgtables", NULL }; char * array declaration might be better as static const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/db899925_66e8845a PS1, Line 108: if (smbios_entry) that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/6445118b_5257c829 PS1, Line 121: if (dt) that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/9918a015_c7843a6a PS1, Line 128: } trailing whitespace File src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/ecb6079e_f0fa6fd0 PS1, Line 104: { CBMEM_ID_FDT, "FDT " }, \ please, no space before tabs File src/include/acpi/acpi.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/7e374195_91501293 PS1, Line 242: u64 lo; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/5bc7d7ca_0b8c7b9b PS1, Line 243: u64 hi; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/f2ec23b2_a842f390 PS1, Line 248: struct { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/cdf4350a_02749940 PS1, Line 249: u32 lhxw : 4; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/1442d56c_f18d6e34 PS1, Line 249: u32 lhxw : 4; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/d455e1ff_25b9feef PS1, Line 250: u32 hhxw : 3; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/6af0080d_78cea8e5 PS1, Line 250: u32 hhxw : 3; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/3a6ccba4_21dd312a PS1, Line 251: u32 lhxs : 3; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/071686b1_5fcb94c3 PS1, Line 251: u32 lhxs : 3; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/35ee80e4_79cdbdc1 PS1, Line 252: u32 hhxs : 5; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/8c2f2c5a_a3409c9b PS1, Line 252: u32 hhxs : 5; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/32f981a6_50c636d4 PS1, Line 253: u32 reserved : 17; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/d6aa2b4a_4a5aa0b5 PS1, Line 253: u32 reserved : 17; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/e32736e3_38119587 PS1, Line 254: }; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/0172e54b_4a8cdf11 PS1, Line 255: u32 hart_index; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/ae35de78_e18651cc PS1, Line 260: struct { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/375dae43_16058072 PS1, Line 261: u64 mmu_type : 4; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/6e56daea_dd1c6cec PS1, Line 261: u64 mmu_type : 4; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/ba2dfe15_afb2f1de PS1, Line 262: u64 aia_enabled : 1; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/84bfadc8_84dfb2df PS1, Line 262: u64 aia_enabled : 1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/ed122753_e0f65282 PS1, Line 263: u64 reserved : 59; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/18be0cb7_342164a9 PS1, Line 263: u64 reserved : 59; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/6ea5781a_72cf3f00 PS1, Line 264: }; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/9853fd06_1cb3b097 PS1, Line 265: u64 hart_cap; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/fa02b7c1_b8fa825e PS1, Line 272: u16 reserved; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/a81bbbac_d959b789 PS1, Line 273: u32 flags; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/32b65db1_b9689c9a PS1, Line 274: u32 parent; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/1c45b044_892e5889 PS1, Line 275: u32 acpi_processor_id; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/220301cd_57b730dd PS1, Line 276: u32 num_private_resources; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/09ce371c_80c46b76 PS1, Line 277: u32 private_resources[]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/b4992dc4_d1d8cb72 PS1, Line 283: u16 reserved; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/24cbeb89_8590c02c PS1, Line 284: u32 flags; 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please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/08641b3e_dece443f PS1, Line 321: u16 ipi_count; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/3cc80ec1_08b07e65 PS1, Line 322: u32 hart_index; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/4da23ceb_527d7ad6 PS1, Line 323: u32 reserved2; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/3e006b9d_2d2dc2e4 PS1, Line 324: AcpiImsicSocket socket_imsic[]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/6fd9e77b_78843bb6 PS1, Line 329: u64 imsic_addr; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/c942026e_c0375221 PS1, Line 330: u32 hart_index; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/0ea5aa6e_257257a6 PS1, Line 331: u16 imsic_size; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/54647cfa_91d6f6fa PS1, Line 332: u16 num_harts; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/cbc94d8d_09e1d6a8 PS1, Line 333: u8 cpuId[]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/01f23e84_31edc36d PS1, Line 338: u8 type; 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please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/8195c0e7_76bb2972 PS1, Line 343: u16 num_interrupts; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/9ac4ecc8_3eb6280f PS1, Line 344: u16 target_imsic; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/ae88d6d5_3ee069a5 PS1, Line 345: u16 reserved; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/536be43e_915e66b1 PS1, Line 346: u16 aplic_size; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/2146019d_2113862b PS1, Line 347: u64 aplic_addr; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/c24a6b23_1bb05fae PS1, Line 348: AcpiAplicImsicInfo imsic_info; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/f6afe02c_98f9ba03 PS1, Line 353: u8 type; \ please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/ee660e5e_80521ee5 PS1, Line 353: u8 type; \ Avoid unnecessary line continuations Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/b78c50fe_1dd947d1 PS1, Line 354: u8 length; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/f44ab135_1290b247 PS1, Line 355: u8 version; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/ffb26f3e_3447489f PS1, Line 356: u8 aia_csr_enabled; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/f70c5e79_dff2d69b PS1, Line 357: u32 acpi_proc_id; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/de26e75b_a7266136 PS1, Line 358: struct Acpi128 hartId; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/6007e709_304e5386 PS1, Line 366: u16 num_mtimer; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/79f8da18_fabe369c PS1, Line 367: u16 num_harts; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/b996767e_5aded49d PS1, Line 368: u32 reserved1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/f9e482fb_1e9ea698 PS1, Line 369: u32 size; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/ac03ad26_615fcada PS1, Line 370: u64 base_addr; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/95311338_4c03720c PS1, Line 371: u64 time_base_frequency; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175115): https://review.coreboot.org/c/coreboot/+/74808/comment/50ecd829_15ff7c83 PS1, Line 372: struct Acpi128 hartId[]; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/74808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3924c15a07960f42753b02fbfbb4df5b0a5a866 Gerrit-Change-Number: 74808 Gerrit-PatchSet: 1 Gerrit-Owner: weidongwd <weidong.wd(a)bytedance.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 12:34:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd: Reserve PCIe MMCONF in ACPI
by Arthur Heymans (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Hello Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74807 to look at the new patch set (#2). Change subject: soc/amd: Reserve PCIe MMCONF in ACPI ...................................................................... soc/amd: Reserve PCIe MMCONF in ACPI Linux complains about this: "[Firmware Info]: PCI: MMCONFIG at [mem 0cf8000000-0xfbffffff] not reserved in ACPI motherboard resources" Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I33e8d7f5057099ffa92853e8df52bb2aee968957 --- M src/soc/amd/cezanne/acpi/pci0.asl M src/soc/amd/glinda/acpi/pci0.asl M src/soc/amd/mendocino/acpi/pci0.asl M src/soc/amd/phoenix/acpi/pci0.asl M src/soc/amd/picasso/acpi/sb_pci0_fch.asl M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl 6 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/74807/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33e8d7f5057099ffa92853e8df52bb2aee968957 Gerrit-Change-Number: 74807 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/meteorlake: Allow option to perform CSE sync at romstage
by Subrata Banik (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Anil Kumar K, Tarun Tuli, Jamie Ryu, Paul Menzel, Kapil Porwal, Sridhar Siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74763 ) Change subject: soc/intel/meteorlake: Allow option to perform CSE sync at romstage ...................................................................... Patch Set 7: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74763/comment/e548bac4_e008ad8a PS3, Line 15: when they choose to : perform CSE FW sync in RAMSTAGE instead. > Why should they want to do that? Why should that use-case be supported? Ack Commit Message: https://review.coreboot.org/c/coreboot/+/74763/comment/51bb0d8d_ccd5ac9b PS5, Line 7: Add config option to choose CSE FW sync in : ROMSTAGE > Use config to perform CSE sync at romstage Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/74763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e603a2ecf1a67ee7c683b440072889d137f9de0 Gerrit-Change-Number: 74763 Gerrit-PatchSet: 7 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 12:34:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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