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Change subject: [WIP] mb/google: Use chromeec_smi_sleep()
......................................................................
[WIP] mb/google: Use chromeec_smi_sleep()
Change-Id: I8a04068dd986f2d5dbebecd0bff08cc0189a34d6
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/mainboard/google/cyan/smihandler.c
M src/mainboard/google/rambi/smihandler.c
M src/mainboard/intel/strago/smihandler.c
3 files changed, 13 insertions(+), 57 deletions(-)
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Change subject: [WIP] mb/google: Re-arrange mainboard_smi_sleep()
......................................................................
[WIP] mb/google: Re-arrange mainboard_smi_sleep()
If we can change the order... can call chromeec handlers
without changes.
Change-Id: I5a10afa2b816dc8c01074be68a63114ee027c1e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/mainboard/google/cyan/smihandler.c
M src/mainboard/google/rambi/smihandler.c
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Change subject: [WIP] mb/google/link: Use chromeec_smi_sleep()
......................................................................
[WIP] mb/google/link: Use chromeec_smi_sleep()
Board did not use MAINBOARD_EC_S5_WAKE attribute before.
With the change keyboard is no longer a wakeup source from
S4/S5.
Change-Id: I54c7d7455a6737f731c65e57c91b6457643c7cb2
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---
M src/mainboard/google/link/smihandler.c
1 file changed, 16 insertions(+), 10 deletions(-)
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Change subject: [WIP] ACPI: Add usb_charge_mode_from_gnvs()
......................................................................
[WIP] ACPI: Add usb_charge_mode_from_gnvs()
Used together with (old API?) of ChromeEC to control
USB port power for S3/S5 sleep states.
This changes adds USB power control for S4 behave the
same as for S5.
Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/acpi/Kconfig
M src/acpi/acpi_pm.c
M src/ec/google/chromeec/smihandler.c
M src/ec/google/chromeec/smm.h
M src/include/acpi/acpi_gnvs.h
M src/mainboard/google/auron/Kconfig
M src/mainboard/google/auron/smihandler.c
M src/mainboard/google/butterfly/Kconfig
M src/mainboard/google/butterfly/smihandler.c
M src/mainboard/google/cyan/Kconfig
M src/mainboard/google/cyan/smihandler.c
M src/mainboard/google/link/Kconfig
M src/mainboard/google/link/smihandler.c
M src/mainboard/google/parrot/Kconfig
M src/mainboard/google/parrot/smihandler.c
M src/mainboard/google/rambi/Kconfig
M src/mainboard/google/rambi/smihandler.c
M src/mainboard/google/slippy/Kconfig
M src/mainboard/google/slippy/smihandler.c
M src/mainboard/google/stout/Kconfig
M src/mainboard/google/stout/smihandler.c
M src/mainboard/intel/strago/Kconfig
M src/mainboard/intel/strago/smihandler.c
M src/soc/intel/broadwell/include/soc/nvs.h
24 files changed, 127 insertions(+), 100 deletions(-)
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Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73212 )
Change subject: mb/google/poppy/variant/nami - Ensure power cycle of FPMCU on startup
......................................................................
Patch Set 7: Code-Review+2
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Change subject: mb/google/poppy: Add support for variant SKU romstage GPIO configs
......................................................................
Patch Set 8: Code-Review+2
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74742 )
Change subject: util/cbmem: Add REG_NEWLINE flag to fix matching pattern
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74742/comment/28e46812_f2ea045c
PS1, Line 13: REG_NEWLINE
> > The only real issue is that the `.?` introduced may match a newline […]
Sure, if you have the time to fix it up please go ahead.
File util/cbmem/cbmem.c:
https://review.coreboot.org/c/coreboot/+/74742/comment/9f778e4d_2d880732
PS2, Line 1010: match.rm_so + 1;
> Never mind. […]
Yeah, the `cursor` variable basically servers double duty between tracking where we need to start scanning for the next pattern and where we want to start printing if we found what we're looking for. The `rm_so + 1` was just an easy way to make it fit both requirements (it will cut off the first `\n` when printing but that doesn't matter in practice). You could split it into two separate tracking variables and then start scanning from `rm_eo` instead, but it didn't seem worth the effort.
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Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74243 )
Change subject: arch/x86: Disable walkcbfs_asm code when CONFIG_CBFS_VERIFICATION is set
......................................................................
arch/x86: Disable walkcbfs_asm code when CONFIG_CBFS_VERIFICATION is set
walkcbfs_asm is a simple CBFS implementation in assembly to find a file
on a system with memory-mapped SPI flash. It seems to be mostly unused
nowadays and is only still called for early microcode loading on some
old systems (e.g. FSP 1.1 and older).
Using this implementation with CONFIG_CBFS_VERIFICATION is unsafe
because it does not verify the hashes the way the normal CBFS code does.
Therefore, to avoid potential security vulnerabilities from creeping in,
this patch makes sure the code cannot be compiled in when
CBFS_VERIFICATION is active. That means it won't be supported on the old
boards using this for microcode loading.
Ideally CONFIG_CBFS_VERIFICATION should have a `depends on` to make this
dependency more obvious in menuconfig, but the configs actually using
this code are not easy to untangle (e.g. CONFIG_MICROCODE_UPDATE_PRE_RAM
is just set everywhere by default although only very few boards are
really using it, and a lot of different old Intel CPU models are linking
in src/cpu/intel/car/non-evict/cache_as_ram.S without being united under
a single Kconfig so that's not easy to change). To keep things simple,
this patch will just prevent the code from being built and result in a
linker error if a bad combination of Kconfigs is used together. Later
patches can clean up the Kconfigs to better wrap that dependency if the
affected boards are still of enough interest to be worth that effort.
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Change-Id: I614a1b05881aa7c1539a7f7f296855ff708db56c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74243
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr>
Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com>
---
M src/arch/x86/Makefile.inc
M src/arch/x86/walkcbfs.S
2 files changed, 44 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Elyes Haouas: Looks good to me, but someone else must approve
Karthik Ramasubramanian: Looks good to me, approved
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index d281037..4ac30ca 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -112,8 +112,10 @@
$(cbfs-autogen-attributes) $(TS_OPTIONS) $(CBFSTOOL_ADD_CMD_OPTIONS)
endif
+ifneq ($(CONFIG_CBFS_VERIFICATION),y)
$(call src-to-obj,bootblock,$(dir)/walkcbfs.S): $(obj)/fmap_config.h
bootblock-y += walkcbfs.S
+endif
endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
diff --git a/src/arch/x86/walkcbfs.S b/src/arch/x86/walkcbfs.S
index 208a128..f4b8d254 100644
--- a/src/arch/x86/walkcbfs.S
+++ b/src/arch/x86/walkcbfs.S
@@ -2,6 +2,10 @@
#include <fmap_config.h>
+#if CONFIG(CBFS_VERIFICATION)
+#error "walkcbfs_asm is not safe to use with CBFS verification!"
+#endif
+
/* we use this instead of CBFS_HEADER_ALIGN because the latter is retired. */
#define CBFS_ALIGNMENT 64
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72931 )
Change subject: soc/intel/cmn/blk: Request pre-reset EC boot timestamps
......................................................................
Patch Set 15: Verified+1
(1 comment)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175166):
https://review.coreboot.org/c/coreboot/+/72931/comment/3357ac98_b5b0ee2d
PS15, Line 13: The EC patches required to enable the feature in the EC:
Possible unwrapped commit description (prefer a maximum 72 chars per line)
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