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Change subject: soc/intel/cmn/block/cse: Implement an API to get ISHC version
......................................................................
Patch Set 3:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74209/comment/ecc8b06c_39ede67f
PS2, Line 7: soc/intel/cmn
> soc/intel/cmd/block/cse
Ack
https://review.coreboot.org/c/coreboot/+/74209/comment/5868eb15_0761511d
PS2, Line 13: ISHC version is verified on the Nissa board using a debug patch
> Able to build and boot google/nivviks. […]
Ack
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/74209/comment/c92ffe3e_ff2aecde
PS2, Line 1215:
> Add a comment saying, this cmd can only work post FSP-M (after CSE DID cmd being sent)
Ack
https://review.coreboot.org/c/coreboot/+/74209/comment/af52b5a2_9202e23a
PS2, Line 1215:
: bool get_ishc_version(struct fw_version *resp_version)
> ``` […]
Ack
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Change subject: mb/google/myst: First pass GPIO configuration for Myst
......................................................................
Patch Set 13:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/74095/comment/9e8bf895_16be84fc
PS11, Line 111: SPI_SOC_DI_FPMCU_DO_R
> I see. Thanks for the explanation. […]
Some of that is scripted. I pinged klug@. We can follow up for consistency.
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74209
to look at the new patch set (#3).
Change subject: soc/intel/cmn/block/cse: Implement an API to get ISHC version
......................................................................
soc/intel/cmn/block/cse: Implement an API to get ISHC version
This patch adds an API that will fetch the current ISHC version from
cbmem. It alerts the user if the current ISHC version is outdated.
BUG=b:273661726
Test=The ISHC version, 5.4.2.7779, was retrieved on the Nissa board.
:
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: Ib3f983d5de5b169474bcdb1e9e2934174a9dadf8
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 54 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/74209/3
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Change subject: mb/google/myst: Enable chromeOS EC
......................................................................
Patch Set 15:
(1 comment)
File src/mainboard/google/myst/ec.c:
https://review.coreboot.org/c/coreboot/+/74099/comment/7b8013c7_5242f26d
PS12, Line 4: #include <console/console.h>
> Not required yet.
Done
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Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69870 )
Change subject: intel/cmn/smm: Introduce PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/smm/Kconfig:
https://review.coreboot.org/c/coreboot/+/69870/comment/f2505adb_4f71230f
PS4, Line 53: Intel Core processors select the periodic SMI rate via GEN_PMCON_A.
> It would probably result in much more code, since you have to implement it for every SOC.
Maybe if the discrepancy was much higher, but for now only the apollolake has been identified with such difference.
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: soc/intel/cmn/block: Store CSE and ISHC version into cbmem table
......................................................................
soc/intel/cmn/block: Store CSE and ISHC version into cbmem table
The patch stores the ISHC and CSE version in the CBMEM table. It
verifies CSE has been updated by comparing old and current CSE versions.
If it has, the patch updates the current CSE version in the CBMEM table.
It then updates the CBMEM table with the current ISHC version.
BUG=b:273661726
Test=The current and old cse and ishc versions are verified on the nissa
during cold and warm reboots. Additionally, version updates are verified
by a debug patch that purposely updated the stored cse version.
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: Ie5c5faf926c75b05d189fb1118020fff024fc3e0
---
M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
3 files changed, 80 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/74208/5
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Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74220 )
Change subject: util/lint/stable-017: Update full config patern matching
......................................................................
util/lint/stable-017: Update full config patern matching
CONFIG_ARCH gives false positives for CONFIG_USE_EXP_X86_64_SUPPORT so
use a different string: 'CONFIG_MAINBOARD_DIR'.
Change-Id: Ie5d4fc4693bc303afb16884c53c9ca4d1778a5cb
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M util/lint/lint-stable-017-configs
1 file changed, 14 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/74220/1
diff --git a/util/lint/lint-stable-017-configs b/util/lint/lint-stable-017-configs
index 3f92f53..5be74457 100755
--- a/util/lint/lint-stable-017-configs
+++ b/util/lint/lint-stable-017-configs
@@ -12,7 +12,7 @@
# shellcheck source=helper_functions.sh
. "${LINTDIR}/helper_functions.sh"
-SYMBOLS='CONFIG_ARCH_\|CONFIG_MAINBOARD_HAS_'
+SYMBOLS='CONFIG_MAINBOARD_DIR\|CONFIG_MAINBOARD_HAS_'
#look for a couple of things that should only be set by select keywords
for file in \
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Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74231 )
Change subject: soc/intel/xeon_sp/acpi: Fix _OSC method
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl:
https://review.coreboot.org/c/coreboot/+/74231/comment/ee57bdaf_6ce3ce67
PS2, Line 56: If (Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc"))
nit: would be good to add back the comment that this GUID is for CXL, as defined in ACPI spec.
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