coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: mb/google/myst: Add new mainboard
by Martin L Roth (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Martin Roth, Fred Reitberger, Tim Van Patten, Karthik Ramasubramanian, Felix Held, Mark Hasemeyer. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74093 ) Change subject: mb/google/myst: Add new mainboard ...................................................................... Patch Set 9: Code-Review+2 (3 comments) Patchset: PS9: Its not perfect, but I think it's good enough of a base for the other patches to start landing. Pretty much everything in this patch still needs to be updated, so I'm completely unconcerned about anything here beyond the fact that it builds. File src/mainboard/google/myst/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/74093/comment/7c3eb59f_2fb3eab7 PS2, Line 2: SI_BIOS { > I'd have to check with the ABL team to know why the APOB increased. For now, I think we just need to accept that the APOB has changed size again and see if we can fix that as the project goes along. File src/mainboard/google/myst/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/74093/comment/01488971_ce33e0e4 PS3, Line 36: } > A 16 MB layout for a first pass should be fine. I'm fine with either 16 or 32, but RO needs to go at the bottom of the rom space. Phoenix will look for the EFS table at 0xff020000. For 16 vs 32MiB, we'll just have to see what fits. I'd be surprised if everything fits in 16MiB initially, but it would definitely be a good surprise. I'd suggest we just go ahead and merge this as it is so that we can start working more on the myst platform instead of trying to get everything perfect on the first commit. -- To view, visit https://review.coreboot.org/c/coreboot/+/74093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7d731ce4d6cb6d4e9041f46eb5a799865bb0b9a Gerrit-Change-Number: 74093 Gerrit-PatchSet: 9 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Wed, 05 Apr 2023 16:47:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/skyrim: override Markarth PCIe config
by John Su (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Jason Nien, Paul Menzel, Chris Wang, Patrick Huang. John Su has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74133 ) Change subject: mb/google/skyrim: override Markarth PCIe config ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74133/comment/c6fc1b19_bfda619b PS3, Line 9: We > lowercase: we Done https://review.coreboot.org/c/coreboot/+/74133/comment/33d9dbbd_7097f054 PS3, Line 12: allows > allowing Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b4e4067a30019d742c7589a52badf93b7091615 Gerrit-Change-Number: 74133 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Huang <patrick.huang(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Patrick Huang <patrick.huang(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 05 Apr 2023 16:46:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/skyrim: override Markarth PCIe config
by John Su (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: John Su, Jason Nien, Paul Menzel, Chris Wang, Patrick Huang. Hello build bot (Jenkins), Jason Nien, Chris Wang, Martin Roth, Karthik Ramasubramanian, Patrick Huang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74133 to look at the new patch set (#4). Change subject: mb/google/skyrim: override Markarth PCIe config ...................................................................... mb/google/skyrim: override Markarth PCIe config Because Markarth PCIe port 1 use for eMMc not SD. So we need override PCIe config for Markarth. And also the Markarth have NVMe and eMMC SKU. Follow Winterhold to look at the NVMe CLKREQ signal before initializing the ports allowing us to identify which device is populated and only initialize that device. BRANCH=none BUG=b:275669215 TEST=emerge-skyrim coreboot chromeos-bootimage Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I0b4e4067a30019d742c7589a52badf93b7091615 --- M src/mainboard/google/skyrim/Kconfig M src/mainboard/google/skyrim/variants/markarth/Makefile.inc A src/mainboard/google/skyrim/variants/markarth/port_descriptors.c 3 files changed, 120 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/74133/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b4e4067a30019d742c7589a52badf93b7091615 Gerrit-Change-Number: 74133 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Huang <patrick.huang(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Patrick Huang <patrick.huang(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/meteorlake: Add VPU into the DMAR SATC table
by John Zhao (Code Review) 05 Apr '23

05 Apr '23

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74221 ) Change subject: soc/intel/meteorlake: Add VPU into the DMAR SATC table ...................................................................... soc/intel/meteorlake: Add VPU into the DMAR SATC table This change adds the VPU into the DMAR SATC table in order to support the VPU IO virtualization. BUG=None TEST=Enabled the VPU, booted to kernel and verified that DMAR SATC table includeded the VPU entry. Change-Id: I6d4af7c9844e33483a1e616eaee061a90d0be6fc Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/meteorlake/acpi.c 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/74221/1 diff --git a/src/soc/intel/meteorlake/acpi.c b/src/soc/intel/meteorlake/acpi.c index c679af3..cbaa694 100644 --- a/src/soc/intel/meteorlake/acpi.c +++ b/src/soc/intel/meteorlake/acpi.c @@ -270,6 +270,7 @@ current += acpi_create_dmar_satc(current, ATC_REQUIRED, 0); current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0); current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IPU, 0); + current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_VPU, 0); acpi_dmar_satc_fixup(tmp, current); return current; -- To view, visit https://review.coreboot.org/c/coreboot/+/74221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d4af7c9844e33483a1e616eaee061a90d0be6fc Gerrit-Change-Number: 74221 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: amd/mendocino/root_complex: Restrict DPTC to 15W boards
by Felix Held (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Tim Van Patten, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74127 ) Change subject: amd/mendocino/root_complex: Restrict DPTC to 15W boards ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94f3974fce6358e3cbb0c30c1af33eb7ecb29ad7 Gerrit-Change-Number: 74127 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 05 Apr 2023 15:32:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/mendocino: Reinterpret smu_power_and_thm_limit
by Felix Held (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Tim Van Patten, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74126 ) Change subject: soc/amd/mendocino: Reinterpret smu_power_and_thm_limit ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I632e702d986a4ac85605040e09c1afab2bbdc59d Gerrit-Change-Number: 74126 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 05 Apr 2023 15:28:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: amd/mendocino/root_complex: Restrict DPTC to 15W boards
by Tim Van Patten (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74127 to look at the new patch set (#4). Change subject: amd/mendocino/root_complex: Restrict DPTC to 15W boards ...................................................................... amd/mendocino/root_complex: Restrict DPTC to 15W boards Restrict DPTC to 15W boards, since we only have 15W values defined in the devicetree. This will revert the 6W boards back to their default values, rather than (incorrectly) configuring them with 15W values. BUG=b:253301653 TEST=Verify DPTC values are set for 15W boards TEST=Verify DPTC values are set not set for 6W boards Change-Id: I94f3974fce6358e3cbb0c30c1af33eb7ecb29ad7 Signed-off-by: Tim Van Patten <timvp(a)google.com> --- M src/soc/amd/mendocino/root_complex.c 1 file changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/74127/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94f3974fce6358e3cbb0c30c1af33eb7ecb29ad7 Gerrit-Change-Number: 74127 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/mendocino: Reinterpret smu_power_and_thm_limit
by Tim Van Patten (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Tim Van Patten, Fred Reitberger. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74126 to look at the new patch set (#5). Change subject: soc/amd/mendocino: Reinterpret smu_power_and_thm_limit ...................................................................... soc/amd/mendocino: Reinterpret smu_power_and_thm_limit The FSP will return the TDP in the format 0xX0000, where 'X' is the value we're interested in. For example: 0xF0000 (15W), 0x60000 (6W). Re-interpret the value so the caller just sees the TDP directly, without needing to re-interpret things themselves. BUG=b:253301653 TEST=Manually verify value is correct Change-Id: I632e702d986a4ac85605040e09c1afab2bbdc59d Signed-off-by: Tim Van Patten <timvp(a)google.com> --- M src/soc/amd/mendocino/fsp_misc_data_hob.c 1 file changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/74126/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/74126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I632e702d986a4ac85605040e09c1afab2bbdc59d Gerrit-Change-Number: 74126 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/mendocino: Reinterpret smu_power_and_thm_limit
by Felix Held (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Tim Van Patten, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74126 ) Change subject: soc/amd/mendocino: Reinterpret smu_power_and_thm_limit ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I632e702d986a4ac85605040e09c1afab2bbdc59d Gerrit-Change-Number: 74126 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 05 Apr 2023 15:19:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/mt8188: set pin drive strength to 8mA for NOR
by Yu-Ping Wu (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Hung-Te Lin, jason-ch chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74064 ) Change subject: soc/mediatek/mt8188: set pin drive strength to 8mA for NOR ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74064/comment/3383ea42_14d3236a PS5, Line 7: set Set File src/soc/mediatek/mt8188/spi.c: https://review.coreboot.org/c/coreboot/+/74064/comment/9cd5e995_99470cba PS5, Line 111: BIOS_WARNING Shouldn't this be an error? -- To view, visit https://review.coreboot.org/c/coreboot/+/74064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8344449f5b34cefcaaee6936e94f7f669c7148b Gerrit-Change-Number: 74064 Gerrit-PatchSet: 5 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Comment-Date: Wed, 05 Apr 2023 15:16:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2023