coreboot-gerrit April 2023

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[M] Change in coreboot[master]: mb/google/myst: Add new mainboard
by Jon Murphy (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Martin Roth, Fred Reitberger, Tim Van Patten, Karthik Ramasubramanian, Felix Held, Mark Hasemeyer. Hello build bot (Jenkins), Raul Rangel, Martin L Roth, Martin Roth, Fred Reitberger, Tim Van Patten, Karthik Ramasubramanian, Felix Held, Mark Hasemeyer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74093 to look at the new patch set (#10). Change subject: mb/google/myst: Add new mainboard ...................................................................... mb/google/myst: Add new mainboard Myst is a new Google mainboard with an AMD Phoenix SOC. BUG=b:270596106 TEST=util/abuild/abuild -t GOOGLE_MYST --clean Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: Id7d731ce4d6cb6d4e9041f46eb5a799865bb0b9a --- A src/mainboard/google/myst/Kconfig A src/mainboard/google/myst/Kconfig.name A src/mainboard/google/myst/Makefile.inc A src/mainboard/google/myst/board_info.txt A src/mainboard/google/myst/bootblock.c A src/mainboard/google/myst/chromeos.fmd A src/mainboard/google/myst/dsdt.asl A src/mainboard/google/myst/mainboard.c A src/mainboard/google/myst/port_descriptors.c A src/mainboard/google/myst/variants/baseboard/devicetree.cb A src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h 11 files changed, 183 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/74093/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/74093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7d731ce4d6cb6d4e9041f46eb5a799865bb0b9a Gerrit-Change-Number: 74093 Gerrit-PatchSet: 10 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Drop devicetree setting X2apic
by Lean Sheng Tan (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Patrick Rudolph, Jonathan Zhang, Daocheng Bu, Johnny Lin, Ziang Wang, Christian Walter, Tim Chu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74185 ) Change subject: soc/intel/xeon_sp/spr: Drop devicetree setting X2apic ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65152b0696a45b62a5629fd95801187354c7a93b Gerrit-Change-Number: 74185 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 05 Apr 2023 19:59:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/xeon_sp/spr: Fix ACPI errors on multi socket systems
by Felix Held (Code Review) 05 Apr '23

05 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74183 ) Change subject: soc/intel/xeon_sp/spr: Fix ACPI errors on multi socket systems ...................................................................... soc/intel/xeon_sp/spr: Fix ACPI errors on multi socket systems Inject ACPI code for all generated ASL templates. This fixes ACPI errors shown in linux when not all sockets are currently plugged in or some have been disabled. Test: Boot Archer City with CONFIG_MAX_SOCKET=4 Change-Id: I9562a37a92c6140a5623db3c8fb5972e6a90aaa4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74183 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Johnny Lin <Johnny_Lin(a)wiwynn.com> --- M src/soc/intel/xeon_sp/spr/soc_acpi.c 1 file changed, 46 insertions(+), 30 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved Johnny Lin: Looks good to me, but someone else must approve diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c index d9d82ac..619e5bb 100644 --- a/src/soc/intel/xeon_sp/spr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c @@ -86,7 +86,8 @@ fadt->x_gpe1_blk.addrh = 0x0; } -static void create_dsdt_iou_pci_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri) +static void create_dsdt_iou_pci_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, + bool stack_enabled) { /* Stacks 0 (TYPE_UBOX_IIO) @@ -105,16 +106,6 @@ acpigen_write_resourcetemplate_header(); - /* - * ACPI spec requires that each bus device (stack) has a valid - * resource template. Disabled devices still need a valid _CRS - * although the values are ignored. The FWTS sanity check does - * not pass when using the HOB stack resources to generate the - * _CRS resource template for disabled stacks, so we provide a - * zeroed resource template to satisfy both the spec and FWTS. - */ - const bool stack_enabled = ri->Personality < TYPE_RESERVED; - /* Bus Resource */ if (stack_enabled) { /* For stack with CXL device, the PCIe bus resource is BusBase only. */ @@ -178,7 +169,7 @@ acpigen_write_resourcetemplate_footer(); } -static void create_dsdt_iou_cxl_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri) +static void create_dsdt_iou_cxl_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled) { /* Stacks 1 .. 5 (TYPE_UBOX_IIO) @@ -194,7 +185,7 @@ acpigen_write_resourcetemplate_header(); - if (ri->Personality < TYPE_RESERVED) { + if (stack_enabled) { /* bus resource, from (BusBase + 1) to BusLimit */ acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase + 1, ri->BusLimit, 0x0, (ri->BusLimit - ri->BusBase)); @@ -229,7 +220,7 @@ acpigen_write_resourcetemplate_footer(); } -static void create_dsdt_dino_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri) +static void create_dsdt_dino_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled) { /* Stacks 8 .. B (TYPE_DINO) @@ -298,7 +289,7 @@ acpigen_write_name(tres); acpigen_write_resourcetemplate_header(); - if (ri->Personality < TYPE_RESERVED) { + if (stack_enabled) { acpigen_resource_word(2, 0xc, 0, 0, bus_base, bus_limit, 0x0, (bus_limit - bus_base + 1)); @@ -327,7 +318,7 @@ } } -static void create_dsdt_ubox_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri) +static void create_dsdt_ubox_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled) { /* Stacks D .. E (TYPE_UBOX) @@ -348,7 +339,7 @@ acpigen_write_name(tres); acpigen_write_resourcetemplate_header(); - if (ri->Personality >= TYPE_RESERVED) + if (!stack_enabled) acpigen_resource_word(2, 0, 0, 0, 0, 0, 0, 0); else if (i == 0) acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusBase, 0x0, 1); @@ -365,12 +356,12 @@ * Add a DSDT ACPI Name field for STACK enable setting. * This is retrieved by the device _STA defined in iiostack.asl */ -static void create_dsdt_stack_sta(uint8_t socket, uint8_t stack, const STACK_RES *ri) +static void create_dsdt_stack_sta(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled) { char stack_sta[16]; snprintf(stack_sta, sizeof(stack_sta), "ST%d%X", socket, stack); - if (ri->Personality >= TYPE_RESERVED) + if (!stack_enabled) acpigen_write_name_integer(stack_sta, ACPI_STATUS_DEVICE_ALL_OFF); else acpigen_write_name_integer(stack_sta, ACPI_STATUS_DEVICE_ALL_ON); @@ -378,6 +369,8 @@ void uncore_inject_dsdt(const struct device *device) { + bool stack_enabled; + /* Only add RTxx entries once. */ if (device->bus->secondary != 0) return; @@ -402,27 +395,28 @@ /* The _CSR generation must match SPR iiostack.asl. */ const IIO_UDS *hob = get_iio_uds(); - /* TODO: DSDT uses CONFIG_MAX_SOCKET while PlatformData.numofIIO is the actual number - of CPUs plugged in, although it doesn't cause serious errors when not all CPUs are - plugged in, they should be in sync. */ - for (uint8_t socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { + /* Iterate over CONFIG_MAX_SOCKET to keep ASL templates and DSDT injection in sync */ + for (uint8_t socket = 0; socket < CONFIG_MAX_SOCKET; ++socket) { for (int stack = 0; stack < MAX_LOGIC_IIO_STACK; ++stack) { const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; + stack_enabled = hob->PlatformData.IIO_resource[socket].Valid && + ri->Personality < TYPE_RESERVED; + printk(BIOS_DEBUG, "%s processing socket: %d, stack: %d, type: %d\n", __func__, socket, stack, ri->Personality); if (stack <= IioStack5) { // TYPE_UBOX_IIO - create_dsdt_iou_pci_resource(socket, stack, ri); - create_dsdt_iou_cxl_resource(socket, stack, ri); - create_dsdt_stack_sta(socket, stack, ri); + create_dsdt_iou_pci_resource(socket, stack, ri, stack_enabled); + create_dsdt_iou_cxl_resource(socket, stack, ri, stack_enabled); + create_dsdt_stack_sta(socket, stack, ri, stack_enabled); } else if (stack >= IioStack8 && stack <= IioStack11) { // TYPE_DINO - create_dsdt_dino_resource(socket, stack, ri); - create_dsdt_stack_sta(socket, stack, ri); + create_dsdt_dino_resource(socket, stack, ri, stack_enabled); + create_dsdt_stack_sta(socket, stack, ri, stack_enabled); } else if (stack == IioStack13) { // TYPE_UBOX - create_dsdt_ubox_resource(socket, stack, ri); - create_dsdt_stack_sta(socket, stack, ri); + create_dsdt_ubox_resource(socket, stack, ri, stack_enabled); + create_dsdt_stack_sta(socket, stack, ri, stack_enabled); } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/74183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9562a37a92c6140a5623db3c8fb5972e6a90aaa4 Gerrit-Change-Number: 74183 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: util/sconfig: Remove unused ioapic and irq keywords
by Lean Sheng Tan (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Martin L Roth, Maximilian Brune, Arthur Heymans, Kyösti Mälkki, Alexander Couzens. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71789 ) Change subject: util/sconfig: Remove unused ioapic and irq keywords ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3fef0bf923ab3f02f3aeed2e55cf662a3dc3a1b Gerrit-Change-Number: 71789 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Wed, 05 Apr 2023 19:00:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: util/inteltool: Add support for Jasper Lake
by Karol Zmyslowski (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Maciej Pijanowski, Michał Żygowski, Jakub Czapiga, Karol Zmyslowski, Stefan Reinauer, Michal Zygowski. Hello build bot (Jenkins), Maciej Pijanowski, Jakub Czapiga, Stefan Reinauer, Michal Zygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73934 to look at the new patch set (#12). Change subject: util/inteltool: Add support for Jasper Lake ...................................................................... util/inteltool: Add support for Jasper Lake Tested on: GW-R86S-P1 Documents: Intel Datasheet: 634545, rev. 001 Document Number: Intel Pentium Silver and Intel Celeron Processor Datasheet, vol. 2 of 2 Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Signed-off-by: Karol Zmyslowski <karol.zmyslowski(a)3mdeb.com> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c A util/inteltool/gpio_names/jasperlake.h M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 6 files changed, 703 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/73934/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/73934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Gerrit-Change-Number: 73934 Gerrit-PatchSet: 12 Gerrit-Owner: Karol Zmyslowski Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Karol Zmyslowski Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: vc/amd/fps/phoenix/platform_descriptors: drop logical-physical mapping
by Felix Held (Code Review) 05 Apr '23

05 Apr '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74223 ) Change subject: vc/amd/fps/phoenix/platform_descriptors: drop logical-physical mapping ...................................................................... vc/amd/fps/phoenix/platform_descriptors: drop logical-physical mapping Phoenix doesn't have different lane numbers in the schematic vs. in the descriptors, so remove that part from the comment on the fsp_dxio_descriptor struct. The start_logical_lane and end_logical_lane fields aren't renamed yet due to the patches updating the DXIO descriptors of the different mainboards still being in review and not being submitted into upstream yet. The fields will be renamed after those have been submitted. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I94664fd9d3807370b73f9fae8645d444e5faf7b7 --- M src/vendorcode/amd/fsp/phoenix/platform_descriptors.h 1 file changed, 21 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/74223/1 diff --git a/src/vendorcode/amd/fsp/phoenix/platform_descriptors.h b/src/vendorcode/amd/fsp/phoenix/platform_descriptors.h index a260138..8abfd3e 100644 --- a/src/vendorcode/amd/fsp/phoenix/platform_descriptors.h +++ b/src/vendorcode/amd/fsp/phoenix/platform_descriptors.h @@ -165,16 +165,10 @@ /* * Phoenix DXIO Descriptor: Used for assigning lanes to PCIe engines, configure - * bifurcation and other settings. Beware that the lane numbers in here are the - * logical and not the physical lane numbers! + * bifurcation and other settings. * - * Phoenix DXIO logical lane to physical PCIe lane mapping: - * - * logical | physical - * ----------|------------ - * PA[00:03] | GPP[03:00] - * PA[04:05] | GPP[08:09] - * PB[00:07] | GPP[12:19] + * TODO: Rename start_logical_lane and end_logical_lane to start_lane and end_lane when the + * updates of the mainboard's DXIO descriptors have been submitted. * * Different ports mustn't overlap or be assigned to the same lane(s). Within * ports with the same width the one with a higher start logical lane number -- To view, visit https://review.coreboot.org/c/coreboot/+/74223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94664fd9d3807370b73f9fae8645d444e5faf7b7 Gerrit-Change-Number: 74223 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: util/inteltool: Add support for Jasper Lake
by Karol Zmyslowski (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Maciej Pijanowski, Michał Żygowski, Jakub Czapiga, Karol Zmyslowski, Stefan Reinauer, Michal Zygowski. Karol Zmyslowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73934 ) Change subject: util/inteltool: Add support for Jasper Lake ...................................................................... Patch Set 10: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/73934/comment/411000ca_0bd4a4be PS9, Line 10: Documents: Intel Datasheet: 633935, rev. 006 > Done Done Patchset: PS10: > Currently, I still apply changes, regarding pointed notes. Done File util/inteltool/gpio_names/jasperlake.h: https://review.coreboot.org/c/coreboot/+/73934/comment/28c26653_1b4ae191 PS9, Line 312: "GSPI0_CLK_LOOPBK", "GSPI0_CLK_LOOPBK", > Ack Done https://review.coreboot.org/c/coreboot/+/73934/comment/5e0e04dd_2a4b80da PS9, Line 317: .display = "------- GPIO Group GPP_B -------", > Ack Done https://review.coreboot.org/c/coreboot/+/73934/comment/21877e04_54e3c1a8 PS9, Line 359: const char *const jasperlake_pch_group_sys_comm2_names[] = { > Ack Done https://review.coreboot.org/c/coreboot/+/73934/comment/e9d477e3_b4ef8cdc PS9, Line 384: const char *const jasperlake_pch_group_sys_pcie_names[] = { > Ack […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/73934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Gerrit-Change-Number: 73934 Gerrit-PatchSet: 10 Gerrit-Owner: Karol Zmyslowski Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Karol Zmyslowski Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Comment-Date: Wed, 05 Apr 2023 17:27:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Comment-In-Reply-To: Karol Zmyslowski Gerrit-MessageType: comment

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[L] Change in coreboot[master]: util/inteltool: Add support for Jasper Lake
by Karol Zmyslowski (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Maciej Pijanowski, Michał Żygowski, Jakub Czapiga, Stefan Reinauer, Michal Zygowski. Hello build bot (Jenkins), Maciej Pijanowski, Jakub Czapiga, Stefan Reinauer, Michal Zygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73934 to look at the new patch set (#11). Change subject: util/inteltool: Add support for Jasper Lake ...................................................................... util/inteltool: Add support for Jasper Lake Tested on: GW-R86S-P1 Documents: Intel Datasheet: 634545, rev. 001 Document Number: Intel Pentium Silver and Intel Celeron Processor Datasheet, vol. 2 of 2 Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Signed-off-by: Karol Zmyslowski <karol.zmyslowski(a)3mdeb.com> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c A util/inteltool/gpio_names/jasperlake.h M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 6 files changed, 703 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/73934/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/73934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Gerrit-Change-Number: 73934 Gerrit-PatchSet: 11 Gerrit-Owner: Karol Zmyslowski Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/myst: First pass GPIO configuration for Myst
by Martin L Roth (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74095 ) Change subject: mb/google/myst: First pass GPIO configuration for Myst ...................................................................... Patch Set 13: Code-Review+2 (1 comment) Patchset: PS13: Good enough for the initial commit. -- To view, visit https://review.coreboot.org/c/coreboot/+/74095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia019704c7b027f14d46281e0de0ffdbc4906a20b Gerrit-Change-Number: 74095 Gerrit-PatchSet: 13 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Wed, 05 Apr 2023 16:49:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/myst: Add new mainboard
by Martin L Roth (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Martin Roth, Fred Reitberger, Tim Van Patten, Karthik Ramasubramanian, Felix Held, Mark Hasemeyer. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74093 ) Change subject: mb/google/myst: Add new mainboard ...................................................................... Patch Set 9: Code-Review+2 (3 comments) Patchset: PS9: Its not perfect, but I think it's good enough of a base for the other patches to start landing. Pretty much everything in this patch still needs to be updated, so I'm completely unconcerned about anything here beyond the fact that it builds. File src/mainboard/google/myst/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/74093/comment/7c3eb59f_2fb3eab7 PS2, Line 2: SI_BIOS { > I'd have to check with the ABL team to know why the APOB increased. For now, I think we just need to accept that the APOB has changed size again and see if we can fix that as the project goes along. File src/mainboard/google/myst/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/74093/comment/01488971_ce33e0e4 PS3, Line 36: } > A 16 MB layout for a first pass should be fine. I'm fine with either 16 or 32, but RO needs to go at the bottom of the rom space. Phoenix will look for the EFS table at 0xff020000. For 16 vs 32MiB, we'll just have to see what fits. I'd be surprised if everything fits in 16MiB initially, but it would definitely be a good surprise. I'd suggest we just go ahead and merge this as it is so that we can start working more on the myst platform instead of trying to get everything perfect on the first commit. -- To view, visit https://review.coreboot.org/c/coreboot/+/74093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7d731ce4d6cb6d4e9041f46eb5a799865bb0b9a Gerrit-Change-Number: 74093 Gerrit-PatchSet: 9 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Wed, 05 Apr 2023 16:47:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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