coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

1 participants
5761 discussions

[S] Change in coreboot[master]: util/testing/Makefile.inc: Fix typo in parameter
by Felix Singer (Code Review) 05 Apr '23

05 Apr '23

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74240 ) Change subject: util/testing/Makefile.inc: Fix typo in parameter ...................................................................... util/testing/Makefile.inc: Fix typo in parameter The test-abuild target fails since a parameter used for scan-build is missing a dash. Fix it. Change-Id: Iae10f639c43fed7709698e620e732cddce5658d8 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M util/testing/Makefile.inc 1 file changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/74240/1 diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc index ff55df0..528b7ec 100644 --- a/util/testing/Makefile.inc +++ b/util/testing/Makefile.inc @@ -116,7 +116,7 @@ test-abuild: ifneq ($(JENKINS_SKIP_SCANBUILD_TEST),y) - NAME=scanbuild; SCANBUILD_ARGS='-k -plist-html -maxloop 10' util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/$${NAME} $(ABUILD_OPTIONS) -scan-build --target EMULATION_QEMU_X86_Q35 --exitcode --name $${NAME} + NAME=scanbuild; SCANBUILD_ARGS='-k -plist-html -maxloop 10' util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/$${NAME} $(ABUILD_OPTIONS) --scan-build --target EMULATION_QEMU_X86_Q35 --exitcode --name $${NAME} endif ifneq ($(JENKINS_SKIP_GCC_TESTS),y) NAME=gcc-chromeos; util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/$${NAME} $(ABUILD_OPTIONS) -x --name $${NAME} --clean -- To view, visit https://review.coreboot.org/c/coreboot/+/74240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae10f639c43fed7709698e620e732cddce5658d8 Gerrit-Change-Number: 74240 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: mb/google/sarien: Use runtime detection for touchscreens
by Matt DeVillier (Code Review) 05 Apr '23

05 Apr '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74239 ) Change subject: mb/google/sarien: Use runtime detection for touchscreens ...................................................................... mb/google/sarien: Use runtime detection for touchscreens Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. TEST=build/boot Windows/linux on drallion, verify touchscreen functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I3b91a628cd4a9edb5d5a7521529f39b75935e1d0 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 22 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/74239/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 52c37df..14df721 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -310,7 +310,7 @@ register "generic.hid" = ""WCOM48E2"" register "generic.desc" = ""Wacom Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" register "generic.reset_delay_ms" = "120" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 1e9d321..b216235 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -322,7 +322,7 @@ register "generic.hid" = ""ELAN900C"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" register "generic.reset_delay_ms" = "10" @@ -339,7 +339,7 @@ register "hid" = ""MLFS0000"" register "desc" = ""Melfas Touchscreen"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" - register "probed" = "1" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" register "reset_delay_ms" = "10" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" -- To view, visit https://review.coreboot.org/c/coreboot/+/74239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b91a628cd4a9edb5d5a7521529f39b75935e1d0 Gerrit-Change-Number: 74239 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: mb/google/sarien: Set touchpad/screen IRQs to LEVEL vs EDGE
by Matt DeVillier (Code Review) 05 Apr '23

05 Apr '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74238 ) Change subject: mb/google/sarien: Set touchpad/screen IRQs to LEVEL vs EDGE ...................................................................... mb/google/sarien: Set touchpad/screen IRQs to LEVEL vs EDGE Ensure the GPIOs themselves are configured as level triggered, as well as the devicetree entiures. I2C-HID spec requires LEVEL trigger, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE trigger. TEST=tested with rest of patch train Change-Id: I4fba55c938f401876798c2b32c5922523f32180f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/sarien/variants/sarien/gpio.c 4 files changed, 22 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/74238/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index ee7fa60..52c37df 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -324,7 +324,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" register "detect" = "1" device i2c 2c on end end diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index 45aed5f..3051e3a 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -39,7 +39,7 @@ /* CORE_VID1 */ /* VRALERT# */ PAD_NC(GPP_B2, NONE), /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ + LEVEL, INVERT), /* TOUCHPAD_INTR# */ /* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ /* LAN_CLKREQ_CPU_N */ /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index f01950e..1e9d321 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -338,7 +338,7 @@ chip drivers/i2c/generic register "hid" = ""MLFS0000"" register "desc" = ""Melfas Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" register "probed" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" register "reset_delay_ms" = "10" @@ -354,7 +354,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" register "detect" = "1" device i2c 2c on end end diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index 5eb5607..d02d69b 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -34,7 +34,7 @@ /* CORE_VID1 */ /* VRALERT# */ PAD_NC(GPP_B2, NONE), /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ + LEVEL, INVERT), /* TOUCHPAD_INTR# */ /* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLKREQ_PCIE#0 */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* CLKREQ_PCIE#1 */ @@ -81,7 +81,7 @@ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ /* UART2_RTS# */ PAD_NC(GPP_C22, NONE), /* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* TS_INT# */ + LEVEL, INVERT), /* TS_INT# */ /* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST, EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74238 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fba55c938f401876798c2b32c5922523f32180f Gerrit-Change-Number: 74238 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: mb/google/sarien: Implement touchscreen power sequencing
by Matt DeVillier (Code Review) 05 Apr '23

05 Apr '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74237 ) Change subject: mb/google/sarien: Implement touchscreen power sequencing ...................................................................... mb/google/sarien: Implement touchscreen power sequencing For touchscreens on sarien, drive the enable GPIO high starting in romstage while holding in reset, then disable the reset GPIO in ramstage. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). BUG=b:121309055 TEST=tested with rest of patch train Change-Id: I3ce7bfc0fa4c03c0bb96bebaa3c3d256f886ecc4 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/sarien/gpio.c 2 files changed, 35 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/74237/1 diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index 63df675..45aed5f 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -242,6 +242,12 @@ /* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ }; +static const struct pad_config romstage_gpio_table[] = { + /* Enable touchscreen, hold in reset */ + PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ + PAD_CFG_GPO(GPP_E7, 0, DEEP), /* TOUCH_SCREEN_PD# */ +}; + const struct pad_config *variant_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); @@ -256,8 +262,8 @@ const struct pad_config *variant_romstage_gpio_table(size_t *num) { - *num = 0; - return NULL; + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; } static const struct cros_gpio cros_gpios[] = { diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index f9797d3..5eb5607 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -230,6 +230,12 @@ /* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ }; +static const struct pad_config romstage_gpio_table[] = { + /* Enable touchscreen, hold in reset */ + PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ + PAD_CFG_GPO(GPP_E7, 0, DEEP), /* TOUCH_SCREEN_PD# */ +}; + const struct pad_config *variant_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); @@ -244,8 +250,8 @@ const struct pad_config *variant_romstage_gpio_table(size_t *num) { - *num = 0; - return NULL; + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; } static const struct cros_gpio cros_gpios[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/74237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ce7bfc0fa4c03c0bb96bebaa3c3d256f886ecc4 Gerrit-Change-Number: 74237 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: mb/google/sarien: Add method to set GPIOs in romstage
by Matt DeVillier (Code Review) 05 Apr '23

05 Apr '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74236 ) Change subject: mb/google/sarien: Add method to set GPIOs in romstage ...................................................................... mb/google/sarien: Add method to set GPIOs in romstage Add method variant_romstage_gpio_table() with empty implementation to be used in a subsequent commit for touchscreen power sequencing. Call method in romstage to program any GPIOs that may need to be set. TEST=tested with rest of patch train Change-Id: I11b72a10a4a105385fbcf1d795c020708a7a90d9 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/sarien/romstage.c M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h M src/mainboard/google/sarien/variants/sarien/gpio.c M src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h 5 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/74236/1 diff --git a/src/mainboard/google/sarien/romstage.c b/src/mainboard/google/sarien/romstage.c index bc0a799..8045112 100644 --- a/src/mainboard/google/sarien/romstage.c +++ b/src/mainboard/google/sarien/romstage.c @@ -3,6 +3,7 @@ #include <ec/google/wilco/romstage.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> +#include <variant/gpio.h> static const struct cnl_mb_cfg memcfg = { /* Access memory info through SMBUS. */ @@ -44,7 +45,13 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { + const struct pad_config *pads; + size_t pads_num; + wilco_ec_romstage_init(); cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); + + pads = variant_romstage_gpio_table(&pads_num); + gpio_configure_pads(pads, pads_num); } diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index fbaeb39..63df675 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -254,6 +254,12 @@ return early_gpio_table; } +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h b/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h index f56059c..0472f60 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h @@ -14,5 +14,6 @@ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); +const struct pad_config *variant_romstage_gpio_table(size_t *num); #endif diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index 7f226e4..f9797d3 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -242,6 +242,12 @@ return early_gpio_table; } +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h b/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h index f56059c..0472f60 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h @@ -14,5 +14,6 @@ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); +const struct pad_config *variant_romstage_gpio_table(size_t *num); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/74236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11b72a10a4a105385fbcf1d795c020708a7a90d9 Gerrit-Change-Number: 74236 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: mb/google/fizz/var/fizz: update VBT
by Matt DeVillier (Code Review) 05 Apr '23

05 Apr '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74235 ) Change subject: mb/google/fizz/var/fizz: update VBT ...................................................................... mb/google/fizz/var/fizz: update VBT Drop fixed resolution at boot, disable eFP. Fixes HDMI audio output under Windows 10/11. TEST=build/boot Win 11 on Fizz, verify HDMI audio now functional. Change-Id: Iecede735bc1266af837e791e6c024aec2f9a8a80 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/fizz/variants/fizz/data.vbt 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/74235/1 diff --git a/src/mainboard/google/fizz/variants/fizz/data.vbt b/src/mainboard/google/fizz/variants/fizz/data.vbt index dbbf475..6679742 100644 --- a/src/mainboard/google/fizz/variants/fizz/data.vbt +++ b/src/mainboard/google/fizz/variants/fizz/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/74235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecede735bc1266af837e791e6c024aec2f9a8a80 Gerrit-Change-Number: 74235 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: mb/google/poppy/var/nami: Fix stylus runtime detection
by Matt DeVillier (Code Review) 05 Apr '23

05 Apr '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74234 ) Change subject: mb/google/poppy/var/nami: Fix stylus runtime detection ...................................................................... mb/google/poppy/var/nami: Fix stylus runtime detection Stylus reset GPIO needs to be held low in romstage, released in ramstage for runtime i2c detection to pick it up. TEST=build/boot AKALI360 variant, verify stylus detected in cbmem, functional in OS. Change-Id: I2e7f2a28f6b3a71b0c8fc367168cffbe3f064663 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/poppy/variants/nami/gpio.c 1 file changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/74234/1 diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c index 8df93f2..68f0f5b 100644 --- a/src/mainboard/google/poppy/variants/nami/gpio.c +++ b/src/mainboard/google/poppy/variants/nami/gpio.c @@ -153,7 +153,7 @@ /* D2 : SPI1_MISO ==> PEN_PDCT# */ PAD_CFG_GPI_APIC_HIGH(GPP_D2, NONE, PLTRST), /* D3 : SPI1_MOSI ==> PEN_RST# */ - PAD_CFG_GPO(GPP_D3, 0, DEEP), + PAD_CFG_GPO(GPP_D3, 1, DEEP), /* D4 : FASHTRIG ==> NC */ PAD_NC(GPP_D4, NONE), /* D5 : ISH_I2C0_SDA ==> NC */ @@ -486,6 +486,9 @@ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* B3 : CPU_GP2 ==> TOUCHSCREEN_RST# */ PAD_CFG_GPO(GPP_B3, 0, DEEP), + /* D3 : SPI1_MOSI ==> PEN_RST# */ + PAD_CFG_GPO(GPP_D3, 0, DEEP), + }; const struct pad_config *variant_romstage_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/74234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e7f2a28f6b3a71b0c8fc367168cffbe3f064663 Gerrit-Change-Number: 74234 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: mb/google/myst: Add new mainboard
by Jon Murphy (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Eric Lai, Martin Roth, Fred Reitberger, Tim Van Patten, Karthik Ramasubramanian, Felix Held, Mark Hasemeyer. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74093 ) Change subject: mb/google/myst: Add new mainboard ...................................................................... Patch Set 10: (4 comments) File src/mainboard/google/myst/Kconfig: https://review.coreboot.org/c/coreboot/+/74093/comment/8f38dd25_61fbc2b9 PS3, Line 8: config AMD_FWM_POSITION_INDEX : int : default 3 > Phoenix has a fixed EFS location (0x20000) so this config value has no effect Done File src/mainboard/google/myst/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/74093/comment/cb815f11_bc90629e PS2, Line 2: SI_BIOS { > I'd have to check with the ABL team to know why the APOB increased. Done File src/mainboard/google/myst/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/74093/comment/39e6bcba_8b3b18d1 PS3, Line 36: } > A 16 MB layout for a first pass should be fine. Opened b/276944900 and added a TODO in the flashmap descriptor File src/mainboard/google/myst/dsdt.asl: https://review.coreboot.org/c/coreboot/+/74093/comment/43ece9e9_441bf63d PS2, Line 16: Name(LIDS, 0) > The LIDS object is used by the EC and not by the SoC. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7d731ce4d6cb6d4e9041f46eb5a799865bb0b9a Gerrit-Change-Number: 74093 Gerrit-PatchSet: 10 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Wed, 05 Apr 2023 20:06:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/brya: Compile gpio.c in SMM
by Matt DeVillier (Code Review) 05 Apr '23

05 Apr '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74233 ) Change subject: mb/google/brya: Compile gpio.c in SMM ...................................................................... mb/google/brya: Compile gpio.c in SMM Necessary for SMMSTORE to work properly. Matches implementation in all previous big-core Intel platform ChromeOS boards (volteer, hatch). TEST=build/boot google/banshee with SMMSTORE support enabled Change-Id: If049cba98f13f060807058029306dcad2ada2d49 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc M src/mainboard/google/brya/variants/baseboard/brya/Makefile.inc M src/mainboard/google/brya/variants/baseboard/hades/Makefile.inc M src/mainboard/google/brya/variants/baseboard/nissa/Makefile.inc 4 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/74233/1 diff --git a/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc index 8a4b2ac..0de0170 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc +++ b/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc @@ -5,3 +5,5 @@ ramstage-y += gpio.c ramstage-y += ramstage.c + +smm-y += gpio.c diff --git a/src/mainboard/google/brya/variants/baseboard/brya/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/brya/Makefile.inc index 8a4b2ac..0de0170 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/Makefile.inc +++ b/src/mainboard/google/brya/variants/baseboard/brya/Makefile.inc @@ -5,3 +5,5 @@ ramstage-y += gpio.c ramstage-y += ramstage.c + +smm-y += gpio.c diff --git a/src/mainboard/google/brya/variants/baseboard/hades/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/hades/Makefile.inc index 7c75e20..ceadd2f 100644 --- a/src/mainboard/google/brya/variants/baseboard/hades/Makefile.inc +++ b/src/mainboard/google/brya/variants/baseboard/hades/Makefile.inc @@ -1,2 +1,5 @@ romstage-y += memory.c + ramstage-y += ramstage.c + +smm-y += gpio.c diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.inc index 8a4b2ac..0de0170 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.inc +++ b/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.inc @@ -5,3 +5,5 @@ ramstage-y += gpio.c ramstage-y += ramstage.c + +smm-y += gpio.c -- To view, visit https://review.coreboot.org/c/coreboot/+/74233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If049cba98f13f060807058029306dcad2ada2d49 Gerrit-Change-Number: 74233 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: mb/google/myst: Enable chromeOS EC
by build bot (Jenkins) (Code Review) 05 Apr '23

05 Apr '23

Attention is currently required from: Raul Rangel, Eric Lai, Mark Hasemeyer. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74099 ) Change subject: mb/google/myst: Enable chromeOS EC ...................................................................... Patch Set 16: (2 comments) File src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173444): https://review.coreboot.org/c/coreboot/+/74099/comment/167b5218_dad0b0cb PS16, Line 71: #define SIO_EC_PS2K_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {1} space prohibited between function name and open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173444): https://review.coreboot.org/c/coreboot/+/74099/comment/85e1abb7_15238927 PS16, Line 71: #define SIO_EC_PS2K_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {1} Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/74099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id18a311097d575973087eb92fd446a5c511f570e Gerrit-Change-Number: 74099 Gerrit-PatchSet: 16 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Wed, 05 Apr 2023 20:04:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2023