coreboot-gerrit April 2023

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[L] Change in coreboot[master]: mb/google/nissa/var/yaviks: Update devicetree setting for yavilla
by Tony Huang (Code Review) 07 Apr '23

07 Apr '23

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74261 ) Change subject: mb/google/nissa/var/yaviks: Update devicetree setting for yavilla ...................................................................... mb/google/nissa/var/yaviks: Update devicetree setting for yavilla Configure devicetree according to yavilla's design. BUG=b:277148122 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I38dbcf5920d12adb1f84885bdfa4c2f2faf2eb9e Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/yaviks/include/variant/gpio.h M src/mainboard/google/brya/variants/yaviks/overridetree.cb 3 files changed, 266 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/74261/1 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index fb8bb5e..0cb71d4 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -295,6 +295,9 @@ select BOARD_GOOGLE_BASEBOARD_NISSA select DRIVERS_GENESYSLOGIC_GL9750 select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_GENERIC_GPIO_KEYS + select DRIVERS_INTEL_MIPI_CAMERA + select HAVE_WWAN_POWER_SEQUENCE config BOARD_GOOGLE_LISBON bool "-> Lisbon" diff --git a/src/mainboard/google/brya/variants/yaviks/include/variant/gpio.h b/src/mainboard/google/brya/variants/yaviks/include/variant/gpio.h index c4fe342..c96b01f 100644 --- a/src/mainboard/google/brya/variants/yaviks/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/yaviks/include/variant/gpio.h @@ -5,4 +5,8 @@ #include <baseboard/gpio.h> +#define WWAN_FCPO GPP_D6 +#define WWAN_RST GPP_F12 +#define T2_OFF_MS 20 + #endif diff --git a/src/mainboard/google/brya/variants/yaviks/overridetree.cb b/src/mainboard/google/brya/variants/yaviks/overridetree.cb index d02b79e..431b0ed 100644 --- a/src/mainboard/google/brya/variants/yaviks/overridetree.cb +++ b/src/mainboard/google/brya/variants/yaviks/overridetree.cb @@ -2,10 +2,28 @@ field DB_USB 0 1 option DB_NONE 0 option DB_1C_1A 1 + option DB_1C 2 + option DB_1C_LTE 3 end field WIFI_SAR_ID 2 3 option SAR_ID_0 0 end + field SD_CARD 9 + option SD_PRESENT 0 + option SD_ABSENT 1 + end + field WFC 10 11 + option WFC_MIPI_ABSENT 0 + option WFC_MIPI_OVTI8856 1 + end + field STYLUS 12 + option STYLUS_ABSENT 0 + option STYLUS_PRESENT 1 + end + field MB_HDMI 13 + option HDMI_ABSENT 0 + option HDMI_PRESENT 1 + end end chip soc/intel/alderlake @@ -63,9 +81,12 @@ register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # USB2 WWAN register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WWAN + # Configure external V1P05/Vnn/VnnSx Rails register "ext_fivr_settings" = "{ .configure_ext_fivr = 1, @@ -79,6 +100,7 @@ #| | required to set up a BAR | #| | for TPM communication | #| I2C1 | Touchscreen | + #| I2C2 | WCAM | #| I2C3 | Audio | #| I2C5 | Trackpad | #+-------------------+---------------------------+ @@ -102,6 +124,15 @@ .sda_hold = 30, } }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, .i2c[3] = { .speed = I2C_SPEED_FAST, .speed_config[0] = { @@ -175,6 +206,20 @@ device generic 0 on end end end + device ref ipu on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "1" + register "cio2_lanes_used" = "{2}" # 2 CSI Camera lanes are used + register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0"" + register "cio2_prt[0]" = "1" + device generic 0 on end + end + probe WFC WFC_MIPI_OVTI8856 + end device ref i2c1 on chip drivers/i2c/hid register "generic.hid" = ""ELAN2513"" @@ -194,6 +239,23 @@ device i2c 10 on end end chip drivers/i2c/hid + register "generic.hid" = ""ELAN900C"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_delay_ms" = "280" + register "generic.stop_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" @@ -208,6 +270,98 @@ register "hid_desc_reg_offset" = "0x01" device i2c 40 on end end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)" + register "key.wake_gpe" = "GPE0_DW2_15" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on + probe STYLUS STYLUS_PRESENT + end + end + end + device ref i2c2 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI8856"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 8856 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + register "has_power_resource" = "1" + + register "ssdb.lanes_used" = "2" + register "ssdb.link_used" = "1" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "2" + register "link_freq[0]" = "720000000" + register "link_freq[1]" = "360000000" + register "remote_name" = ""IPU0"" + + #Controls + register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" + register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X + register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1800_PP1200_WCAM_X + register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" # WCAM_RST_L + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 10 on + probe WFC WFC_MIPI_OVTI8856 + end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF DAC"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + device i2c 0C on + probe WFC WFC_MIPI_OVTI8856 + end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""GT24C08"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" + + register "nvm_size" = "0x2000" + register "nvm_pagesize" = "1" + register "nvm_readonly" = "1" + register "nvm_width" = "0x10" + register "nvm_compat" = ""atmel,24c08"" + + device i2c 50 on + probe WFC WFC_MIPI_OVTI8856 + end + end end device ref i2c3 on chip drivers/i2c/generic @@ -232,8 +386,18 @@ register "detect" = "1" device i2c 15 on end end + chip drivers/i2c/hid + register "generic.hid" = ""SYNA0000"" + register "generic.cid" = ""ACPI0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end end - device ref hda on + device ref hda on chip drivers/generic/max98357a register "hid" = ""MX98360A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" @@ -254,6 +418,21 @@ device pci 00.0 on end end end + device ref pcie_rp7 on + # Enable SD Card PCIe 7 using clk 3 + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H12)" + register "srcclk_pin" = "3" + device generic 0 on end + end + probe SD_CARD SD_PRESENT + end device ref emmc on end device ref ish on chip drivers/intel/ish @@ -323,16 +502,47 @@ device ref usb2_port2 on end end chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port3 on + probe DB_USB DB_1C + probe DB_USB DB_1C_LTE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port4 on + probe DB_USB DB_1C + probe DB_USB DB_1C_LTE + end + end + chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A1 (DB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" - device ref usb2_port4 on end + device ref usb2_port4 on + probe DB_USB DB_1C_1A + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on + probe DB_USB DB_1C_LTE + end end chip drivers/usb/acpi register "desc" = ""USB2 UFC"" register "type" = "UPC_TYPE_INTERNAL" - device ref usb2_port6 on end + device ref usb2_port6 on + probe WFC WFC_MIPI_OVTI8856 + end end chip drivers/usb/acpi register "desc" = ""USB2 Bluetooth"" @@ -349,11 +559,40 @@ device ref usb2_port10 on end end chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port1 on + probe DB_USB DB_1C + probe DB_USB DB_1C_LTE + end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port2 on + probe DB_USB DB_1C + probe DB_USB DB_1C_LTE + end + end + chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A1 (DB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" - device ref usb3_port1 on end + device ref usb3_port2 on + probe DB_USB DB_1C_1A + end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port3 on + probe DB_USB DB_1C_LTE + end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/74261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38dbcf5920d12adb1f84885bdfa4c2f2faf2eb9e Gerrit-Change-Number: 74261 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/myst: Enable tis_plat_irq_status
by build bot (Jenkins) (Code Review) 07 Apr '23

07 Apr '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74286 ) Change subject: mb/google/myst: Enable tis_plat_irq_status ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173642): https://review.coreboot.org/c/coreboot/+/74286/comment/021221fc_72a2741d PS1, Line 9: This will fix: Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/74286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I611a2855d94167748d0f82a478687fe2cdf5846a Gerrit-Change-Number: 74286 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 Apr 2023 05:22:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Enable tis_plat_irq_status
by Jon Murphy (Code Review) 07 Apr '23

07 Apr '23

Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74286 ) Change subject: mb/google/myst: Enable tis_plat_irq_status ...................................................................... mb/google/myst: Enable tis_plat_irq_status This will fix: > [INFO ] Probing TPM I2C: tis_plat_irq_status() not implemented, wasting 20ms to wait on Cr50! BUG=b:277297687 TEST=builds Change-Id: I611a2855d94167748d0f82a478687fe2cdf5846a --- M src/mainboard/google/myst/variants/baseboard/Makefile.inc A src/mainboard/google/myst/variants/baseboard/tpm_tis.c 2 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/74286/1 diff --git a/src/mainboard/google/myst/variants/baseboard/Makefile.inc b/src/mainboard/google/myst/variants/baseboard/Makefile.inc index 40a41df..ffa462a 100644 --- a/src/mainboard/google/myst/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/myst/variants/baseboard/Makefile.inc @@ -1,7 +1,11 @@ bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += tpm_tis.c romstage-y += gpio.c +romstage-y += tpm_tis.c + +verstage-y += tpm_tis.c smm-y += smihandler.c diff --git a/src/mainboard/google/myst/variants/baseboard/tpm_tis.c b/src/mainboard/google/myst/variants/baseboard/tpm_tis.c new file mode 100644 index 0000000..42accfa --- /dev/null +++ b/src/mainboard/google/myst/variants/baseboard/tpm_tis.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <security/tpm/tis.h> +#include <soc/gpio.h> + +int tis_plat_irq_status(void) +{ + return gpio_interrupt_status(GPIO_84); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/74286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I611a2855d94167748d0f82a478687fe2cdf5846a Gerrit-Change-Number: 74286 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/brya: Enable asynchronous End-Of-Post
by Subrata Banik (Code Review) 07 Apr '23

07 Apr '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74215 ) Change subject: mb/google/brya: Enable asynchronous End-Of-Post ...................................................................... mb/google/brya: Enable asynchronous End-Of-Post Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post right after PCI enumeration and handle the command response at `BS_PAYLOAD_BOOT'. With these settings we have observed a boot time reduction of about 20 to 30 ms on brya0. BUG=b:268546941 BRANCH=firmware-brya-14505.B TEST=Tests on brya0 with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post after PCI initialization and EOP message received at `BS_PAYLOAD_BOOT'. Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Change-Id: Ib850330fbb9e84839eb1093db054332cbcb59b41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74215 Reviewed-by: Tarun Tuli <taruntuli(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/Kconfig M src/soc/intel/alderlake/Kconfig 2 files changed, 29 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Jérémy Compostella: Looks good to me, but someone else must approve Tarun Tuli: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 9ae944d..e588524 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -32,6 +32,7 @@ select PMC_IPC_ACPI_INTERFACE select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_CSE_SEND_EOP_ASYNC select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES if SOC_INTEL_ALDERLAKE_PCH_P select SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE select SOC_INTEL_CRASHLOG diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 1bc84ce..2887439 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -122,7 +122,7 @@ select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET - select SOC_INTEL_CSE_SEND_EOP_LATE + select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select HAVE_INTEL_COMPLIANCE_TEST_MODE -- To view, visit https://review.coreboot.org/c/coreboot/+/74215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib850330fbb9e84839eb1093db054332cbcb59b41 Gerrit-Change-Number: 74215 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: soc/intel/cmn/cse: Handle EOP completion asynchronously
by Subrata Banik (Code Review) 07 Apr '23

07 Apr '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74214 ) Change subject: soc/intel/cmn/cse: Handle EOP completion asynchronously ...................................................................... soc/intel/cmn/cse: Handle EOP completion asynchronously coreboot supports three instances of sending EOP: 1. At CSE `.final' device operation 2. Early as with Alder Lake in chip_operations.init if `SOC_INTEL_CSE_SEND_EOP_EARLY' is selected 3. At BS_PAYLOAD_BOOT as designed for Meteor Lake if `SOC_INTEL_CSE_SEND_EOP_LATE' is selected Currently, Alder Lake uses #3 as it results in better and more stable boot time. However, what would deliver even better result is to not actively wait for CSE completion. This patch introduces a new `SOC_INTEL_CSE_SEND_EOP_ASYNC' Kconfig which split the action of sending EOP request and receiving EOP completion response from the CSE. This patch used in conjunction with #1 can significantly improves the overall boot time on a Raptor Lake design. For example `SOC_INTEL_CSE_SEND_EOP_ASYNC' on a skolas board can deliver up to 36 ms boot time improvement as illustrated below. | # | Late EOP | Async EOP | |----------+----------+-----------| | 1 | 1020.052 | 971.272 | | 2 | 1015.911 | 971.821 | | 3 | 1038.415 | 1021.841 | | 4 | 1020.657 | 993.751 | | 5 | 1065.128 | 1020.951 | | 6 | 1037.859 | 1023.326 | | 7 | 1042.010 | 984.412 | |----------+----------+-----------| | Mean | 1034.29 | 998.20 | | Variance | 4.76 % | 5.21 % | The improvement is not stable but comparing coreboot and FSP performance timestamps demonstrate that the slowness is caused by a lower memory frequency (SaGv point) at early boot which is not an issue addressed by this patch. We also observe some improvement on an Alder Lake design. For example, the same configuration on a kano board can deliver up to 10 ms boot time improvement as illustrated below. | # | Late EOP | Async EOP | |----------+----------+-----------| | 0 | 1067.719 | 1050.106 | | 1 | 1058.263 | 1056.836 | | 2 | 1064.091 | 1056.709 | | 3 | 1068.614 | 1055.042 | | 4 | 1065.749 | 1056.732 | | 5 | 1069.838 | 1057.846 | | 6 | 1066.897 | 1053.548 | | 7 | 1060.850 | 1051.911 | |----------+----------+-----------| | Mean | 1065.25 | 1054.84 | The improvement is more limited on kano because a longer PCIe initialization delays EOP in the Late EOP configuration which make it faster to complete. CSME team confirms that: 1. End-Of-Post is a blocking command in the sense that BIOS is requested to wait for the command completion before loading the OS or second stage bootloader. 2. The BIOS is not required to actively wait for completion of the command and can perform other operations in the meantime as long as they do not involve HECI commands. On Raptor Lake, coreboot does not send any HECI command after End-Of-Post. FSP-s code review did not reveal any HECI command being sent as part of the `AFTER_PCI_ENUM', `READY_TO_BOOT' or `END_OF_FIRMWARE' notifications. If any HECI send and receive command has been sent the extra code added in `cse_receive_eop()' should catch it. According to commit 387ec919d9f7 ("soc/intel/alderlake: Select SOC_INTEL_CSE_SEND_EOP_LATE"), FSP-silicon can sometimes (on the first boot after flashing of a Marasov board for instance) request coreboot to perform a global request out of AFTER_PCI_ENUM notification. Global request relies on a HECI command. Even though, we tested that it does not create any issue, `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag should not be associated to the `SOC_INTEL_CSE_SEND_EOP_EARLY' flag to prevent potential a global reset command to "conflict" with the EOP command. This patch also introduces a new code logic to detect if CSE is in the right state to handle the EOP command. Otherwise, it uses the prescribed method to make the CSE function disable. The typical scenario is the ChromeOS recovery boot where CSE stays in RO partition and therefore EOP command should be avoided. [DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 14 ms [INFO ] HECI: coreboot in recovery mode; found CSE in expected SOFT TEMP DISABLE state, skipping EOP [INFO ] Disabling Heci using PMC IPC [WARN ] HECI: CSE device 16.0 is hidden [WARN ] HECI: CSE device 16.1 is disabled [WARN ] HECI: CSE device 16.2 is disabled [WARN ] HECI: CSE device 16.3 is disabled [WARN ] HECI: CSE device 16.4 is disabled [WARN ] HECI: CSE device 16.5 is disabled BUG=b:276339544 BRANCH=firmware-brya-14505.B TEST=Tests on brya0 with and `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post sent soon after FSP-s and EOP message receive at `BS_PAYLOAD_BOOT'. Verify robustness by injecting a `GET_BOOT_STATE' HECI command with or without `heci_reset'. The implementation always successfully completed the EOP before moving to the payload. As expected, the boot time benefit of the asynchronous solution was under some injection scenario undermined by this unexpected HECI command. Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I01a56bfe3f6c37ffb5e51a527d9fe74785441c5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/74214 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_eop.c 3 files changed, 260 insertions(+), 45 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Jérémy Compostella: Looks good to me, but someone else must approve Tarun Tuli: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index f1f53d6..33d703f 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -67,6 +67,25 @@ Starting with Jasper Lake, coreboot sends EOP before loading payload hence, this config is applicable for those platforms. +config SOC_INTEL_CSE_SEND_EOP_ASYNC + bool + depends on SOC_INTEL_COMMON_BLOCK_CSE + depends on !SOC_INTEL_CSE_SEND_EOP_LATE + depends on !SOC_INTEL_CSE_SEND_EOP_EARLY + help + Use this config to handle End Of Post (EOP) completion + asynchronously. The EOP command is sent first and the result + is checked later leaving time to CSE to complete the + operation while coreboot perform other activities. + Performing EOP asynchronously reduces the time spent + actively waiting for command completion which can have a + significant impact on boot time. + + Using this asynchronous approach comes with the limitation + that no HECI command should be sent between the time the EOP + request is posted (at CSE .final device operation) and the + time coreboot check for its completion (BS_PAYLOAD_LOAD). + config SOC_INTEL_CSE_LITE_SKU bool default n diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 9902094..6c4bb73 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1407,7 +1407,8 @@ */ void cse_late_finalize(void) { - if (!CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE)) + if (!CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE) && + !CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) return; if (!CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT)) @@ -1431,6 +1432,14 @@ if (CONFIG(SOC_INTEL_CSE_SET_EOP)) cse_send_end_of_post(); + /* + * In asynchronous mode, the EOP command has most likely not been + * completed yet. Finalization steps will be run once the EOP command + * has successfully been completed. + */ + if (CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) + return; + if (!CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT)) cse_final_ready_to_boot(); diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index 53a4fa5..dd67e59 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -67,13 +67,54 @@ return CSE_CMD_RESULT_SUCCESS; } -static enum cse_cmd_result cse_send_eop(void) +static enum cse_cmd_result cse_receive_eop(void) { - enum cse_tx_rx_status ret; enum { EOP_REQUESTED_ACTION_CONTINUE = 0, EOP_REQUESTED_ACTION_GLOBAL_RESET = 1, }; + enum cse_tx_rx_status ret; + struct end_of_post_resp { + struct mkhi_hdr hdr; + uint32_t requested_actions; + } __packed resp = {}; + size_t resp_size = sizeof(resp); + + ret = heci_receive(&resp, &resp_size); + if (ret) + return decode_heci_send_receive_error(ret); + + if (resp.hdr.group_id != MKHI_GROUP_ID_GEN || + resp.hdr.command != MKHI_END_OF_POST) { + printk(BIOS_ERR, "HECI: EOP Unexpected response group or command.\n"); + if (CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) + printk(BIOS_ERR, "HECI: It could be a HECI command conflict.\n"); + return CSE_CMD_RESULT_ERROR; + } + + if (resp.hdr.result) { + printk(BIOS_ERR, "HECI: EOP Resp Failed: %u\n", resp.hdr.result); + return CSE_CMD_RESULT_ERROR; + } + + printk(BIOS_INFO, "CSE: EOP requested action: "); + + switch (resp.requested_actions) { + case EOP_REQUESTED_ACTION_GLOBAL_RESET: + printk(BIOS_INFO, "global reset\n"); + return CSE_CMD_RESULT_GLOBAL_RESET_REQUESTED; + case EOP_REQUESTED_ACTION_CONTINUE: + printk(BIOS_INFO, "continue boot\n"); + return CSE_CMD_RESULT_SUCCESS; + default: + printk(BIOS_INFO, "unknown %u\n", resp.requested_actions); + return CSE_CMD_RESULT_ERROR; + } +} + +static enum cse_cmd_result cse_send_eop(void) +{ + enum cse_tx_rx_status ret; struct end_of_post_msg { struct mkhi_hdr hdr; } __packed msg = { @@ -82,21 +123,6 @@ .command = MKHI_END_OF_POST, }, }; - struct end_of_post_resp { - struct mkhi_hdr hdr; - uint32_t requested_actions; - } __packed resp = {}; - size_t resp_size = sizeof(resp); - - /* For a CSE-Lite SKU, if the CSE is running RO FW and the board is - running vboot in recovery mode, the CSE is expected to be in SOFT - TEMP DISABLE state. */ - if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && vboot_recovery_mode_enabled() && - cse_is_hfs1_com_soft_temp_disable()) { - printk(BIOS_INFO, "HECI: coreboot in recovery mode; found CSE in expected SOFT " - "TEMP DISABLE state, skipping EOP\n"); - return CSE_CMD_RESULT_SUCCESS; - } /* * Prerequisites: @@ -119,28 +145,22 @@ printk(BIOS_INFO, "HECI: Sending End-of-Post\n"); - ret = heci_send_receive(&msg, sizeof(msg), &resp, &resp_size, HECI_MKHI_ADDR); + ret = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR); if (ret) return decode_heci_send_receive_error(ret); - if (resp.hdr.result) { - printk(BIOS_ERR, "HECI: EOP Resp Failed: %u\n", resp.hdr.result); - return CSE_CMD_RESULT_ERROR; - } + return CSE_CMD_RESULT_SUCCESS; +} - printk(BIOS_INFO, "CSE: EOP requested action: "); +static enum cse_cmd_result cse_send_and_receive_eop(void) +{ + enum cse_cmd_result ret; - switch (resp.requested_actions) { - case EOP_REQUESTED_ACTION_GLOBAL_RESET: - printk(BIOS_INFO, "global reset\n"); - return CSE_CMD_RESULT_GLOBAL_RESET_REQUESTED; - case EOP_REQUESTED_ACTION_CONTINUE: - printk(BIOS_INFO, "continue boot\n"); - return CSE_CMD_RESULT_SUCCESS; - default: - printk(BIOS_INFO, "unknown %u\n", resp.requested_actions); - return CSE_CMD_RESULT_ERROR; - } + ret = cse_send_eop(); + if (ret != CSE_CMD_RESULT_SUCCESS) + return ret; + + return cse_receive_eop(); } static enum cse_cmd_result cse_send_cmd_retries(enum cse_cmd_result (*cse_send_command)(void)) @@ -199,11 +219,12 @@ } } -static void do_send_end_of_post(void) +static void do_send_end_of_post(bool wait_for_completion) { - static bool eop_sent = false; + static bool eop_sent = false, eop_complete = false; + enum cse_cmd_result ret; - if (eop_sent) { + if (eop_complete) { printk(BIOS_WARNING, "EOP already sent\n"); return; } @@ -222,26 +243,65 @@ return; } - set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE); + if (!eop_sent) { + set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE); + timestamp_add_now(TS_ME_END_OF_POST_START); + ret = cse_send_cmd_retries(cse_send_eop); + if (ret == CSE_CMD_RESULT_SUCCESS) + eop_sent = true; + } - timestamp_add_now(TS_ME_END_OF_POST_START); - handle_cse_eop_result(cse_send_cmd_retries(cse_send_eop)); + if (!wait_for_completion) + return; + + set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE); + ret = cse_receive_eop(); + if (ret != CSE_CMD_RESULT_SUCCESS) { + ret = cse_send_cmd_retries(cse_send_and_receive_eop); + handle_cse_eop_result(ret); + } timestamp_add_now(TS_ME_END_OF_POST_END); set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE); - eop_sent = true; + eop_complete = true; +} + +/* + * Don't send EOP if the following conditions are met: + * 1. "The platform is running CSE-Lite SKU" AND + * 2. 'The CSE is running the RO FW" AND + * 3. "The board is in recovery mode" + * + * The above conditions summarize that the CSE is in "SOFT TEMP DISABLE" state, + * hence, don't send the EOP command to CSE. + */ +static bool is_cse_eop_supported(void) +{ + if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && vboot_recovery_mode_enabled() && + cse_is_hfs1_com_soft_temp_disable()) { + printk(BIOS_INFO, "HECI: coreboot in recovery mode; found CSE in expected SOFT " + "TEMP DISABLE state, skipping EOP\n"); + return false; + } + return true; } void cse_send_end_of_post(void) { - return do_send_end_of_post(); + if (!is_cse_eop_supported()) + return; + + return do_send_end_of_post(!CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)); } static void send_cse_eop_with_late_finalize(void *unused) { - do_send_end_of_post(); - if (CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE)) + if (is_cse_eop_supported()) + do_send_end_of_post(true); + + if (CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE) || + CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) cse_late_finalize(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/74214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01a56bfe3f6c37ffb5e51a527d9fe74785441c5a Gerrit-Change-Number: 74214 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/myst: Enable chromeOS EC
by build bot (Jenkins) (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Mark Hasemeyer. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74099 ) Change subject: mb/google/myst: Enable chromeOS EC ...................................................................... Patch Set 18: Verified+1 (2 comments) File src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173611): https://review.coreboot.org/c/coreboot/+/74099/comment/5b1f42a9_4b55948d PS18, Line 71: #define SIO_EC_PS2K_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {1} space prohibited between function name and open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173611): https://review.coreboot.org/c/coreboot/+/74099/comment/ca668a8a_10b7e5a6 PS18, Line 71: #define SIO_EC_PS2K_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {1} Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/74099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id18a311097d575973087eb92fd446a5c511f570e Gerrit-Change-Number: 74099 Gerrit-PatchSet: 18 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Fri, 07 Apr 2023 04:48:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Disable keyboard reset pin
by Jon Murphy (Code Review) 07 Apr '23

07 Apr '23

Jon Murphy has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/74285 ) Change subject: mb/google/myst: Disable keyboard reset pin ...................................................................... mb/google/myst: Disable keyboard reset pin The keyboard reset is not being used on this board, so disable the functionality. BUG=b:277294460 TEST=None Change-Id: If7fb9ab0c9b1260d342313badb65c55bb9f788c0 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M src/mainboard/google/myst/Kconfig 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/74285/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74285 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7fb9ab0c9b1260d342313badb65c55bb9f788c0 Gerrit-Change-Number: 74285 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/myst: Store XHCI PCI resources
by Jon Murphy (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Jon Murphy. Hello build bot (Jenkins), Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74281 to look at the new patch set (#3). Change subject: mb/google/myst: Store XHCI PCI resources ...................................................................... mb/google/myst: Store XHCI PCI resources Implement `smm_mainboard_pci_resource_store_init` to store the resources for XHCI devices. These stored resources are later used by the elog code to log XHCI wake events. BUG=b:277273428 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I608d51f438681ac529323c23cc707845a3d609d1 --- M src/mainboard/google/myst/mainboard.c 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/74281/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I608d51f438681ac529323c23cc707845a3d609d1 Gerrit-Change-Number: 74281 Gerrit-PatchSet: 3 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/myst: Enable S0ix
by Jon Murphy (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Jon Murphy. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74279 to look at the new patch set (#3). Change subject: mb/google/myst: Enable S0ix ...................................................................... mb/google/myst: Enable S0ix Enable s0ix on Myst. BUG=b:277215113 TEST=builds Change-Id: I3cabc2c3ba75f4490da18b861ef2b82ce240860d Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M src/mainboard/google/myst/variants/baseboard/devicetree.cb 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/74279/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cabc2c3ba75f4490da18b861ef2b82ce240860d Gerrit-Change-Number: 74279 Gerrit-PatchSet: 3 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/phoenix: Update XHCI events
by Jon Murphy (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Matt DeVillier, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74280 to look at the new patch set (#3). Change subject: soc/amd/phoenix: Update XHCI events ...................................................................... soc/amd/phoenix: Update XHCI events Set up SoC-specific XHCI defines and enable SOC_AMD_COMMON_BLOCK_XHCI to allow for XHCI events to be logged. BUG=b:277273428 TEST=builds Change-Id: I3ca4f84fb0f1fef8441ab6ef7b6f6348c52b2922 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M src/soc/amd/phoenix/Kconfig A src/soc/amd/phoenix/include/soc/xhci.h M src/soc/amd/phoenix/xhci.c 3 files changed, 37 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/74280/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ca4f84fb0f1fef8441ab6ef7b6f6348c52b2922 Gerrit-Change-Number: 74280 Gerrit-PatchSet: 3 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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