coreboot-gerrit April 2023

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[M] Change in coreboot[master]: mb/amd/birman: Add support for 32M flash
by build bot (Jenkins) (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Bao Zheng, Jason Glenesk, Zheng Bao, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72963 ) Change subject: mb/amd/birman: Add support for 32M flash ...................................................................... Patch Set 8: Verified+1 (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173600): https://review.coreboot.org/c/coreboot/+/72963/comment/12d99df8_a74459b9 PS8, Line 8: Possible repeated word: 'the' -- To view, visit https://review.coreboot.org/c/coreboot/+/72963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0306321f1452e4439a58e3bc5a197a614fce756 Gerrit-Change-Number: 72963 Gerrit-PatchSet: 8 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 07 Apr 2023 04:26:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: WIP: Add xlate_windows to mmap 32M flash
by build bot (Jenkins) (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Zheng Bao, Fred Reitberger, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74260 ) Change subject: WIP: Add xlate_windows to mmap 32M flash ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/spi/spi_map_big.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173604): https://review.coreboot.org/c/coreboot/+/74260/comment/3f2a6761_94c6ee84 PS1, Line 149: printk(BIOS_DEBUG, "bios_mmap_init: 2\n"); Prefer using '"%s...", __func__' to using 'bios_mmap_init', this function's name, in a string -- To view, visit https://review.coreboot.org/c/coreboot/+/74260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd2bf1390635494443cac9ee8600a4a741a78c0d Gerrit-Change-Number: 74260 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 07 Apr 2023 04:26:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: WIP: Add xlate_windows to mmap 32M flash
by Bao Zheng (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Zheng Bao, Fred Reitberger, Felix Held. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/74260 to review the following change. Change subject: WIP: Add xlate_windows to mmap 32M flash ...................................................................... WIP: Add xlate_windows to mmap 32M flash Use SPI ROM page to switch pages. This is one of series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: Ibd2bf1390635494443cac9ee8600a4a741a78c0d Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/common/block/spi/Kconfig M src/soc/amd/common/block/spi/Makefile.inc A src/soc/amd/common/block/spi/spi_map_big.c 3 files changed, 236 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/74260/1 diff --git a/src/soc/amd/common/block/spi/Kconfig b/src/soc/amd/common/block/spi/Kconfig index 7a300e4..85a60fc 100644 --- a/src/soc/amd/common/block/spi/Kconfig +++ b/src/soc/amd/common/block/spi/Kconfig @@ -100,3 +100,10 @@ 3: 16.66MHz 4: 100MHz 5: 800KHz + +config SOC_AMD_COMMON_BLOCK_SPI_MAP_BIG + bool + select X86_CUSTOM_BOOTMEDIA + depends on !SOC_AMD_PICASSO && !SOC_AMD_STONEYRIDGE + help + Select this option to enable SPI more than 16M bytes. diff --git a/src/soc/amd/common/block/spi/Makefile.inc b/src/soc/amd/common/block/spi/Makefile.inc index 55ca308..37d7169 100644 --- a/src/soc/amd/common/block/spi/Makefile.inc +++ b/src/soc/amd/common/block/spi/Makefile.inc @@ -22,4 +22,11 @@ verstage-y += fch_spi_util.c smm-$(CONFIG_SPI_FLASH_SMM) += fch_spi_util.c +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_SPI_MAP_BIG) += spi_map_big.c +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_SPI_MAP_BIG) += spi_map_big.c +postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_SPI_MAP_BIG) += spi_map_big.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_SPI_MAP_BIG) += spi_map_big.c +verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_SPI_MAP_BIG) += spi_map_big.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_SPI_MAP_BIG) += spi_map_big.c + endif # CONFIG_SOC_AMD_COMMON_BLOCK_SPI diff --git a/src/soc/amd/common/block/spi/spi_map_big.c b/src/soc/amd/common/block/spi/spi_map_big.c new file mode 100644 index 0000000..8d8e0c1 --- /dev/null +++ b/src/soc/amd/common/block/spi/spi_map_big.c @@ -0,0 +1,207 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * This file provides a custom boot media device for the platforms that support additional + * window for BIOS regions greater than 16MiB. If the mainboard uses a smaller BIOS region, then + * the additional window is unused. + */ + +#include <boot_device.h> +#include <commonlib/region.h> +#include <console/console.h> +#include <fmap.h> +#include <string.h> +#include <spi_flash.h> +#include <amdblocks/spi.h> + +#define rom_base ((void *)(uintptr_t)(0x100000000ULL-0x1000000)) + +enum window_type { + /* Fixed decode window of max 16MiB size just below 4G boundary */ + FIXED_DECODE_WINDOW, + /* Additional decode window for mapping BIOS region greater than 16MiB */ + EXT_BIOS_DECODE_WINDOW, + TOTAL_DECODE_WINDOWS, +}; + +static struct xlate_region_device real_dev; +static struct mem_region_device shadow_devs[TOTAL_DECODE_WINDOWS]; +static struct xlate_window real_dev_windows[TOTAL_DECODE_WINDOWS]; + +static void *spi_amd_mmap(const struct region_device *rd, size_t offset, + size_t size) +{ + const struct mem_region_device *mdev; + + spi_write32(SPI_ROM_PAGE, 0); + + mdev = container_of(rd, __typeof__(*mdev), rdev); + return &mdev->base[offset]; +} + +static void *spi_amd_mmap_p1(const struct region_device *rd, size_t offset, + size_t size) +{ + const struct mem_region_device *mdev; + + spi_write32(SPI_ROM_PAGE, 1); + + mdev = container_of(rd, __typeof__(*mdev), rdev); + return &mdev->base[offset]; +} + +static int spi_amd_munmap(const struct region_device *rd __always_unused, + void *mapping __always_unused) +{ + /* The FSP takes the assumption that the ROM page is 0. */ + spi_write32(SPI_ROM_PAGE, 0); + + return 0; +} + +static ssize_t spi_amd_readat(const struct region_device *rd, void *b, size_t offset, + size_t size) +{ + const struct mem_region_device *mdev; + + spi_write32(SPI_ROM_PAGE, 0); + + mdev = container_of(rd, __typeof__(*mdev), rdev); + memcpy(b, &mdev->base[offset], size); + + return size; +} + +static ssize_t spi_amd_readat_p1(const struct region_device *rd, void *b, size_t offset, + size_t size) +{ + const struct mem_region_device *mdev; + + spi_write32(SPI_ROM_PAGE, 1); + + mdev = container_of(rd, __typeof__(*mdev), rdev); + memcpy(b, &mdev->base[offset], size); + + spi_write32(SPI_ROM_PAGE, 0); + return size; +} + +const struct region_device_ops spi_amd_rdev_ro_ops = { + .mmap = spi_amd_mmap, + .munmap = spi_amd_munmap, + .readat = spi_amd_readat, +}; + +const struct region_device_ops spi_amd_rdev_ro_ops_p1 = { + .mmap = spi_amd_mmap_p1, + .munmap = spi_amd_munmap, + .readat = spi_amd_readat_p1, +}; + +static const struct mem_region_device boot_dev_top = { + .base = rom_base, + .rdev = REGION_DEV_INIT(&spi_amd_rdev_ro_ops_p1, 0, 0x1000000), +}; + +static const struct mem_region_device boot_dev_bottom = { + .base = rom_base, + .rdev = REGION_DEV_INIT(&spi_amd_rdev_ro_ops, 0, 0x1000000), +}; + +static void initialize_window_top(enum window_type type, uintptr_t host_base, + uintptr_t flash_base, size_t size) +{ + xlate_window_init(&real_dev_windows[type], &boot_dev_top.rdev, + flash_base, size); +} + +static void initialize_window_bottom(enum window_type type, uintptr_t host_base, + uintptr_t flash_base, size_t size) +{ + xlate_window_init(&real_dev_windows[type], &boot_dev_bottom.rdev, + flash_base, size); +} + +static void bios_mmap_init(void) +{ + static bool init_done = false; + + uintptr_t fixed_win_host_base, fixed_win_flash_base; + uintptr_t ext_win_host_base, ext_win_flash_base; + size_t fixed_win_size, ext_win_size; + + size_t win_count = 0; + + if (init_done) + return; + + /* Read the offset and size of BIOS region in the SPI flash address space. */ + //bios_start = fast_spi_get_bios_region(&bios_size); + + /* + * By default, fixed decode window (maximum size 16MiB) is mapped just below the 4G + * boundary. This window maps the top part of the BIOS region in the SPI flash address + * space to the host address space. + */ + fixed_win_size = 16 * MiB; + fixed_win_host_base = 4ULL * GiB - fixed_win_size; + fixed_win_flash_base = 0x0; + printk(BIOS_DEBUG, "bios_mmap_init: 2\n"); + + initialize_window_bottom(FIXED_DECODE_WINDOW, fixed_win_host_base, fixed_win_flash_base, fixed_win_size); + win_count++; + + //_Static_assert(CONFIG_EXT_BIOS_WIN_BASE != 0, "Extended BIOS window base cannot be 0!"); + //_Static_assert(CONFIG_EXT_BIOS_WIN_SIZE != 0, "Extended BIOS window size cannot be 0!"); + + /* + * Remaining portion of the BIOS region up to a maximum of CONFIG_EXT_BIOS_WIN_SIZE is + * mapped at the top of the extended window if the BIOS region is greater than 16MiB. + * + * If the BIOS region is not greater than 16MiB, then the extended window is not + * enabled. + */ + ext_win_size = 16 * MiB; + + if (ext_win_size) { + ext_win_host_base = 0xff000000; + ext_win_flash_base = 0x1000000; + initialize_window_top(EXT_BIOS_DECODE_WINDOW, ext_win_host_base, + ext_win_flash_base, ext_win_size); + win_count++; + } + + xlate_region_device_ro_init(&real_dev, win_count, real_dev_windows, CONFIG_ROM_SIZE); + + init_done = true; +} + +const struct region_device *boot_device_ro(void) +{ + bios_mmap_init(); + + return &real_dev.rdev; +} + +uint32_t spi_flash_get_mmap_windows(struct flash_mmap_window *table) +{ + int i; + uint32_t count = 0; + + bios_mmap_init(); + + for (i = 0; i < TOTAL_DECODE_WINDOWS; i++) { + + if (region_sz(&real_dev_windows[i].sub_region) == 0) + continue; + + count++; + table->flash_base = region_offset(&real_dev_windows[i].sub_region); + table->host_base = (uintptr_t)rdev_mmap_full(&shadow_devs[i].rdev); + table->size = region_sz(&real_dev_windows[i].sub_region); + + table++; + } + + return count; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/74260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd2bf1390635494443cac9ee8600a4a741a78c0d Gerrit-Change-Number: 74260 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: fmap/region: Call the munmap of access_dev in xlate_windows
by Bao Zheng (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/74259 to review the following change. Change subject: fmap/region: Call the munmap of access_dev in xlate_windows ...................................................................... fmap/region: Call the munmap of access_dev in xlate_windows Change-Id: I73f2f78d64a521b6da613228339e09065e37be88 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/commonlib/region.c 1 file changed, 23 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/74259/1 diff --git a/src/commonlib/region.c b/src/commonlib/region.c index 4153f0a..41662e1 100644 --- a/src/commonlib/region.c +++ b/src/commonlib/region.c @@ -369,17 +369,20 @@ return rdev_mmap(xlwindow->access_dev, offset, size); } -static int xlate_munmap(const struct region_device *rd __always_unused, - void *mapping __always_unused) +static int xlate_munmap(const struct region_device *rd, + void *mapping) { - /* - * xlate_region_device does not keep track of the access device that was used to service - * a mmap request. So, munmap does not do anything. If munmap functionality is required, - * then xlate_region_device will have to be updated to accept some pre-allocated space - * from caller to keep track of the mapping requests. Since xlate_region_device is only - * used for memory mapped boot media on the backend right now, skipping munmap is fine. - */ - return 0; + /* TODO: Call the access_dev munmap */ + const struct xlate_region_device *xldev; + const struct xlate_window *xlwindow; + + xldev = container_of(rd, __typeof__(*xldev), rdev); + + xlwindow = &xldev->window_arr[0]; + if (!xlwindow) + return 0; + + return rdev_munmap(xlwindow->access_dev, mapping); } static ssize_t xlate_readat(const struct region_device *rd, void *b, -- To view, visit https://review.coreboot.org/c/coreboot/+/74259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73f2f78d64a521b6da613228339e09065e37be88 Gerrit-Change-Number: 74259 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd: Add definition of SPI ROM remapping
by Bao Zheng (Code Review) 07 Apr '23

07 Apr '23

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[S] Change in coreboot[master]: demo. 32m
by Bao Zheng (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Bao Zheng, Jason Glenesk, Zheng Bao, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Zheng Bao, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72964 to look at the new patch set (#5). Change subject: demo. 32m ...................................................................... demo. 32m Change-Id: I684e6b803c4e2882d1cab71fb9e2974cb9dd68d4 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/amd/birman/Kconfig M src/mainboard/amd/birman/board_phoenix_32M.fmd M src/mainboard/amd/birman/chromeos_phoenix_32M.fmd M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/Makefile.inc 5 files changed, 20 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/72964/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/72964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I684e6b803c4e2882d1cab71fb9e2974cb9dd68d4 Gerrit-Change-Number: 72964 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/myst: Store XHCI PCI resources
by Eric Lai (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Jon Murphy. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74281 ) Change subject: mb/google/myst: Store XHCI PCI resources ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/mainboard/google/myst/mainboard.c: https://review.coreboot.org/c/coreboot/+/74281/comment/27e1decf_6d001ea4 PS1, Line 100: soc_xhci_store_resources(slots, size); > After looking at it further, my guess is that it was set up this way because most of the functionali […] I am fine here. We can clean up later on. I don't have skyrim or guybrush to verify. But I believe keep in soc/amd/common/block/xhci/xhci.c is totally working fine. -- To view, visit https://review.coreboot.org/c/coreboot/+/74281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I608d51f438681ac529323c23cc707845a3d609d1 Gerrit-Change-Number: 74281 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Comment-Date: Fri, 07 Apr 2023 03:59:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Store XHCI PCI resources
by Jon Murphy (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Eric Lai. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74281 ) Change subject: mb/google/myst: Store XHCI PCI resources ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/myst/mainboard.c: https://review.coreboot.org/c/coreboot/+/74281/comment/3364c8b2_ba8abfe2 PS1, Line 100: soc_xhci_store_resources(slots, size); > Good question. […] After looking at it further, my guess is that it was set up this way because most of the functionality lives in the x86 folder, but soc_xhci_store_resources is in the AMD code. It may be worth looking into more, but I think for now I'd like to land it as is -- To view, visit https://review.coreboot.org/c/coreboot/+/74281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I608d51f438681ac529323c23cc707845a3d609d1 Gerrit-Change-Number: 74281 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 07 Apr 2023 03:50:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Store XHCI PCI resources
by Jon Murphy (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Eric Lai. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74281 ) Change subject: mb/google/myst: Store XHCI PCI resources ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/myst/mainboard.c: https://review.coreboot.org/c/coreboot/+/74281/comment/840de249_3d3a40af PS1, Line 100: soc_xhci_store_resources(slots, size); > Just curious, I trace the code a little bit. […] Good question. I admittedly was carrying the implementation forward, but see now that it's a copy/paste across all mainboards. I don't see a reason not to put it in the common code. -- To view, visit https://review.coreboot.org/c/coreboot/+/74281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I608d51f438681ac529323c23cc707845a3d609d1 Gerrit-Change-Number: 74281 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 07 Apr 2023 03:43:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/intel: add Archer City CRB support
by Johnny Lin (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Simon Chou, Paul Menzel, Shuming Chu (Shuming), Arthur Heymans, Lean Sheng Tan, Juan Sanchez, Shelly Chang. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: add Archer City CRB support ...................................................................... Patch Set 29: (1 comment) File src/mainboard/intel/archercity_crb/romstage.c: https://review.coreboot.org/c/coreboot/+/71968/comment/52341b7d_94915af6 PS27, Line 124: mupd->FspmConfig.serialDebugMsgLvl = 0x1; > Hi Johnny/ Shelly, […] In our current design we use VPD to configure FSP log level as well under xeon_sp/spr: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… I think we can remove line 115 to 119 for FSP log level and let VPD to configure them. Another point is that the SPR FSP log level mapping may not be the same as Client FSP log level mappings. -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 29 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-CC: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-CC: Juan Sanchez Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Juan Sanchez Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Comment-Date: Fri, 07 Apr 2023 03:16:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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coreboot-gerrit April 2023