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Change subject: mb/google/myst: Store XHCI PCI resources
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/myst/mainboard.c:
https://review.coreboot.org/c/coreboot/+/74281/comment/51f88fb3_df30402c
PS1, Line 100: soc_xhci_store_resources(slots, size);
Just curious, I trace the code a little bit. This is totally can put in SoC common code since the different parameter is defined by Kconfig which is SMM_PCI_RESOURCE_STORE_NUM_SLOTS and no override. Why put in mainboard?
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Change subject: mb/google/myst: Add smihandler
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Patch Set 20: Code-Review+2
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Change subject: mb/google/myst: First pass GPIO configuration for Myst
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Patch Set 16: Code-Review+2
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Change subject: mb/google/myst: Add new mainboard
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Patch Set 11: Code-Review+2
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Change subject: mb/google/myst: Enable eSPI SCI events
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Patch Set 20: Code-Review+2
(1 comment)
File src/mainboard/google/myst/mainboard.c:
https://review.coreboot.org/c/coreboot/+/74101/comment/57a6ca80_1a352048
PS19, Line 44: pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1)));
> Does that mean the line itself is unnecessary? […]
oh I mean the TODO.
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Change subject: mb/google/myst: Add initial I2C configuration
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Patch Set 24: Code-Review+2
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Change subject: mb/google/myst: Add FW_CONFIG
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Patch Set 22: Code-Review+2
(1 comment)
File src/mainboard/google/myst/variants/myst/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/74102/comment/446f8d39_a256ec13
PS4, Line 20:
> EMMC's are on a bayhub nvme bridge, and for the most part to us they're just slightly different nvme […]
I see it's fair.
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Change subject: mb/google/brya/variants/hades: Update GPU power sequencing to add Hades support
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Patch Set 22:
(1 comment)
Patchset:
PS22:
Do you want merge first or wait verify this?
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Change subject: mb/acer/aspire_vn7_572g: Fix internal speakers again
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/73869/comment/b03b0e4c_6ce6a4e5
PS1, Line 15: Further investigation required to know why this works.
> Do you have a coreboot log before and after this change?
There's no change in the logs about Azalia, which makes sense. The verbs are simply sent to the HDA's "immediate command" register. I may need to see if the HDA device or its BAR have some detailed status reporting register. I don't fully expect it though.
Patchset:
PS1:
> Need to retest the display (HDMI) audio now.
Noticed speakers crackle once again, but seems fine now. Will continue watching.
I've assumed the board is fine. The speaker hardware part should be fine, the firmware should be fine: because unless I'm missing some other module in my analysis, this table is as correct as the vendor's, since it's what is sent to the hardware.
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