coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

1 participants
5761 discussions

[L] Change in coreboot[master]: mb/intel: Add 2 SPR sockets CRB Archer City
by Shelly Chang (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Patrick Rudolph, Simon Chou, Johnny Lin, Paul Menzel, Shuming Chu (Shuming), Arthur Heymans, Lean Sheng Tan, Juan Sanchez. Shelly Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: Add 2 SPR sockets CRB Archer City ...................................................................... Patch Set 31: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/71968/comment/08aae3a9_45262e68 PS29, Line 7: add Archer City CRB support > Maybe mention the type: Add 2 SPR sockets CRB Archer City Done Patchset: PS28: > The multisocket support depends on Change-Id: Ie682bfa376d699c0eee8de0752cd6ae6d8d81fee Done File src/mainboard/intel/archercity_crb/romstage.c: https://review.coreboot.org/c/coreboot/+/71968/comment/2c8ec3e7_e1d41f19 PS27, Line 124: mupd->FspmConfig.serialDebugMsgLvl = 0x1; > In our current design we use VPD to configure FSP log level as well under xeon_sp/spr: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 31 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-CC: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-CC: Juan Sanchez Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Juan Sanchez Gerrit-Comment-Date: Fri, 07 Apr 2023 05:26:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: mb/intel: Add 2 SPR sockets CRB Archer City
by Shelly Chang (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Simon Chou, Paul Menzel, Shuming Chu (Shuming), Arthur Heymans, Lean Sheng Tan, Juan Sanchez, Shelly Chang. Shelly Chang has uploaded a new patch set (#31) to the change originally created by Simon Chou. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: Add 2 SPR sockets CRB Archer City ...................................................................... mb/intel: Add 2 SPR sockets CRB Archer City Intel Archer City CRB is a dual socket CRB with Intel Sapphire Rapids Scalable Processor chipset. The chipset also includes Emmitsburg PCH. It was tested with LinuxBoot payload on both dual and single socket configurations. The multisocket support depends on Change-Id: Ie682bfa376d699c0eee8de0752cd6ae6d8d81fee Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com> Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- A src/mainboard/intel/archercity_crb/Kconfig A src/mainboard/intel/archercity_crb/Kconfig.name A src/mainboard/intel/archercity_crb/Makefile.inc A src/mainboard/intel/archercity_crb/acpi/platform.asl A src/mainboard/intel/archercity_crb/board.fmd A src/mainboard/intel/archercity_crb/board_info.txt A src/mainboard/intel/archercity_crb/bootblock.c A src/mainboard/intel/archercity_crb/devicetree.cb A src/mainboard/intel/archercity_crb/dsdt.asl A src/mainboard/intel/archercity_crb/include/mainboard_ras.h A src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h A src/mainboard/intel/archercity_crb/ramstage.c A src/mainboard/intel/archercity_crb/romstage.c 13 files changed, 483 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/71968/31 -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 31 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-CC: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-CC: Juan Sanchez Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Juan Sanchez Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: mb/google/myst: Enable tis_plat_irq_status
by Jon Murphy (Code Review) 07 Apr '23

07 Apr '23

Jon Murphy has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/74286 ) Change subject: mb/google/myst: Enable tis_plat_irq_status ...................................................................... mb/google/myst: Enable tis_plat_irq_status This will fix: > [INFO ] Probing TPM I2C: tis_plat_irq_status() not implemented, wasting 20ms to wait on Cr50! BUG=b:277297687 TEST=builds Change-Id: I611a2855d94167748d0f82a478687fe2cdf5846a Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M src/mainboard/google/myst/variants/baseboard/Makefile.inc A src/mainboard/google/myst/variants/baseboard/tpm_tis.c 2 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/74286/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I611a2855d94167748d0f82a478687fe2cdf5846a Gerrit-Change-Number: 74286 Gerrit-PatchSet: 3 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: mb/google/myst: Enable tis_plat_irq_status
by build bot (Jenkins) (Code Review) 07 Apr '23

07 Apr '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74286 ) Change subject: mb/google/myst: Enable tis_plat_irq_status ...................................................................... Patch Set 2: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173646): https://review.coreboot.org/c/coreboot/+/74286/comment/11e44cc8_0f02b89d PS2, Line 9: This will fix: Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/74286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I611a2855d94167748d0f82a478687fe2cdf5846a Gerrit-Change-Number: 74286 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 Apr 2023 05:23:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: mb/intel: Add 2 SPR sockets CRB Archer City
by build bot (Jenkins) (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Simon Chou, Paul Menzel, Shuming Chu (Shuming), Arthur Heymans, Lean Sheng Tan, Juan Sanchez, Shelly Chang. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: Add 2 SPR sockets CRB Archer City ...................................................................... Patch Set 30: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173645): https://review.coreboot.org/c/coreboot/+/71968/comment/45596757_366a5da1 PS30, Line 12: configurations. Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 30 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-CC: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-CC: Juan Sanchez Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Juan Sanchez Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Comment-Date: Fri, 07 Apr 2023 05:23:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/nissa/var/yaviks: Select VBT based on FW_CONFIG for yavilla
by build bot (Jenkins) (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Tarun Tuli. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74262 ) Change subject: mb/google/nissa/var/yaviks: Select VBT based on FW_CONFIG for yavilla ...................................................................... Patch Set 1: (10 comments) File src/mainboard/google/brya/variants/yaviks/variant.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173644): https://review.coreboot.org/c/coreboot/+/74262/comment/96085e02_a14c3c7f PS1, Line 21: if (fw_config_probe(FW_CONFIG(MB_HDMI, HDMI_PRESENT))) { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173644): https://review.coreboot.org/c/coreboot/+/74262/comment/692fae6a_2ffdc55d PS1, Line 21: if (fw_config_probe(FW_CONFIG(MB_HDMI, HDMI_PRESENT))) { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173644): https://review.coreboot.org/c/coreboot/+/74262/comment/c463810e_84375831 PS1, Line 22: printk(BIOS_INFO, "Use vbt-yavilla.bin\n"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173644): https://review.coreboot.org/c/coreboot/+/74262/comment/ac90895a_33e12677 PS1, Line 22: printk(BIOS_INFO, "Use vbt-yavilla.bin\n"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173644): https://review.coreboot.org/c/coreboot/+/74262/comment/cbd54459_034274ac PS1, Line 23: return "vbt-yavilla.bin"; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173644): https://review.coreboot.org/c/coreboot/+/74262/comment/86867840_1d0fa3f6 PS1, Line 23: return "vbt-yavilla.bin"; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173644): https://review.coreboot.org/c/coreboot/+/74262/comment/5bbc35f3_8a27a25a PS1, Line 24: } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173644): https://review.coreboot.org/c/coreboot/+/74262/comment/b4adf82f_e4c2f1ce PS1, Line 24: } please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173644): https://review.coreboot.org/c/coreboot/+/74262/comment/b4256a1c_05bf5d4a PS1, Line 25: printk(BIOS_INFO, "Use vbt.bin\n"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173644): https://review.coreboot.org/c/coreboot/+/74262/comment/9168c6fd_47c68f8f PS1, Line 25: printk(BIOS_INFO, "Use vbt.bin\n"); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/74262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I210003c27c83155dd5a768c1a6cdcfd8c849d256 Gerrit-Change-Number: 74262 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Comment-Date: Fri, 07 Apr 2023 05:22:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/myst: Enable tis_plat_irq_status
by Jon Murphy (Code Review) 07 Apr '23

07 Apr '23

Jon Murphy has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/74286 ) Change subject: mb/google/myst: Enable tis_plat_irq_status ...................................................................... mb/google/myst: Enable tis_plat_irq_status This will fix: > [INFO ] Probing TPM I2C: tis_plat_irq_status() not implemented, wasting 20ms to wait on Cr50! BUG=b:277297687 TEST=builds Change-Id: I611a2855d94167748d0f82a478687fe2cdf5846a Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M src/mainboard/google/myst/variants/baseboard/Makefile.inc A src/mainboard/google/myst/variants/baseboard/tpm_tis.c 2 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/74286/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I611a2855d94167748d0f82a478687fe2cdf5846a Gerrit-Change-Number: 74286 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

[L] Change in coreboot[master]: mb/intel: Add 2 SPR sockets CRB Archer City
by Shelly Chang (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Simon Chou, Paul Menzel, Shuming Chu (Shuming), Arthur Heymans, Lean Sheng Tan, Juan Sanchez, Shelly Chang. Shelly Chang has uploaded a new patch set (#30) to the change originally created by Simon Chou. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: Add 2 SPR sockets CRB Archer City ...................................................................... mb/intel: Add 2 SPR sockets CRB Archer City Intel Archer City CRB is a dual socket CRB with Intel Sapphire Rapids Scalable Processor chipset. The chipset also includes Emmitsburg PCH. It was tested with LinuxBoot payload on both dual and single socket configurations. The multisocket support depends on Change-Id: Ie682bfa376d699c0eee8de0752cd6ae6d8d81fee Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com> Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- A src/mainboard/intel/archercity_crb/Kconfig A src/mainboard/intel/archercity_crb/Kconfig.name A src/mainboard/intel/archercity_crb/Makefile.inc A src/mainboard/intel/archercity_crb/acpi/platform.asl A src/mainboard/intel/archercity_crb/board.fmd A src/mainboard/intel/archercity_crb/board_info.txt A src/mainboard/intel/archercity_crb/bootblock.c A src/mainboard/intel/archercity_crb/devicetree.cb A src/mainboard/intel/archercity_crb/dsdt.asl A src/mainboard/intel/archercity_crb/include/mainboard_ras.h A src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h A src/mainboard/intel/archercity_crb/ramstage.c A src/mainboard/intel/archercity_crb/romstage.c 13 files changed, 482 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/71968/30 -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 30 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-CC: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-CC: Juan Sanchez Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Juan Sanchez Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: mb/google/nissa/var/yaviks: Select VBT based on FW_CONFIG for yavilla
by Tony Huang (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Tarun Tuli. Hello Tarun Tuli, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74262 to look at the new patch set (#2). Change subject: mb/google/nissa/var/yaviks: Select VBT based on FW_CONFIG for yavilla ...................................................................... mb/google/nissa/var/yaviks: Select VBT based on FW_CONFIG for yavilla Select hdmi vbt bin files based on MB_HDMI field of FW_CONFIG. BUG=b:277148122 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I210003c27c83155dd5a768c1a6cdcfd8c849d256 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/yaviks/variant.c 1 file changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/74262/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I210003c27c83155dd5a768c1a6cdcfd8c849d256 Gerrit-Change-Number: 74262 Gerrit-PatchSet: 2 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: mb/google/nissa/var/yaviks: Select VBT based on FW_CONFIG for yavilla
by Tony Huang (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Tarun Tuli. Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74262 ) Change subject: mb/google/nissa/var/yaviks: Select VBT based on FW_CONFIG for yavilla ...................................................................... mb/google/nissa/var/yaviks: Select VBT based on FW_CONFIG for yavilla Select hdmi vbt bin files based on MB_HDMI field of FW_CONFIG. BUG=b:277148122 TEST=emerge-nissa coreboot Change-Id: I210003c27c83155dd5a768c1a6cdcfd8c849d256 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/yaviks/variant.c 1 file changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/74262/1 diff --git a/src/mainboard/google/brya/variants/yaviks/variant.c b/src/mainboard/google/brya/variants/yaviks/variant.c index 7010520..265a544 100644 --- a/src/mainboard/google/brya/variants/yaviks/variant.c +++ b/src/mainboard/google/brya/variants/yaviks/variant.c @@ -2,7 +2,9 @@ #include <baseboard/variants.h> #include <boardid.h> +#include <console/console.h> #include <device/device.h> +#include <drivers/intel/gma/opregion.h> #include <fw_config.h> #include <sar.h> @@ -14,6 +16,16 @@ return NULL; } +const char *mainboard_vbt_filename(void) +{ + if (fw_config_probe(FW_CONFIG(MB_HDMI, HDMI_PRESENT))) { + printk(BIOS_INFO, "Use vbt-yavilla.bin\n"); + return "vbt-yavilla.bin"; + } + printk(BIOS_INFO, "Use vbt.bin\n"); + return "vbt.bin"; +} + void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { const uint32_t id = board_id(); -- To view, visit https://review.coreboot.org/c/coreboot/+/74262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I210003c27c83155dd5a768c1a6cdcfd8c849d256 Gerrit-Change-Number: 74262 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newchange

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2023