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Change subject: binaryPI: Use common code for LAPIC NMIs
......................................................................
Patch Set 1: Code-Review+2
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Change subject: ACPI: Add helper for MADT LAPICs
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/74312/comment/f18a8772_b6258507
PS2, Line 150: 0xff
nit: is this worth a `#define` for, e.g. MAX_APIC_ID ?
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Change subject: mb/google/rex: Add DTT thermal settings for thermal control
......................................................................
Patch Set 7: Code-Review+2
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Hello build bot (Jenkins), Tarun Tuli, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74256
to look at the new patch set (#7).
Change subject: soc/intel/: Store CSE firmware version into cbmem table
......................................................................
soc/intel/: Store CSE firmware version into cbmem table
The patch implements an API that stores the CSE firmware version in the
CBMEM table. The API will be called either from RAMSTAGE or ROMSTAGE
based on underlying platform.
BUG=b:273661726
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8
---
M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
M src/soc/intel/alderlake/romstage/romstage.c
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
4 files changed, 62 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/74256/7
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Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74288 )
Change subject: soc/amd/common/blk/pcie: Program LTR max latencies
......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/common/block/pci/pcie_gpp.c:
https://review.coreboot.org/c/coreboot/+/74288/comment/17a7ffe2_2aa39edb
PS1, Line 51: PCIE_LTR_MAX_LATENCY_1047US
> Intel uses the same value for all 6th-13th gen SoCs; Meteorlake is the first to deviate from that. […]
IMHO Kconfig provides the flexibility for future change. But I am fine either way.
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74229 )
Change subject: mb/google/rex: Update Flash Layout to fit WP_RO within 4MB
......................................................................
Patch Set 5:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74229/comment/9a55efe3_c61639b1
PS1, Line 9: This patch updates the Rex flash layout to optimize WP_RO to 4MB.
> > The board was apparently added with 8 MB, so why is it too big now? What optimization is done?
>
> Sorry, I'm still unable to understand what details, u would like to know? we had goal to drop WP_RO from 8MB to 4MB at some point of the program and now we are doing so.
i have updated the commit section to add the motivation towards this change.
https://review.coreboot.org/c/coreboot/+/74229/comment/c15524fe_d350ea87
PS1, Line 9: This patch updates the Rex flash layout to optimize WP_RO to 4MB.
:
: Changes for chromeos.fmd:
:
: SI_BIOS:
: RW_SECTION_A/B: Reduce to 7MB.
: RW_LEGACY: Reduce to 1MB.
: RW_MISC: Increased to 1MB.
: RW_UNUSED: 3MB (reserved)
: WP_RO: Reduce to 4MB
:
: Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the
: SPI Flash.
> > I am sorry you are feeling this way.
>
> I would like to understand if your intention is code review, then please help on that part. I'm feeling like, u are suggesting something which is not possible and I have explained why so, but still this conversation continues
@Paul, marking as done. please let me know otherwise.
File src/mainboard/google/rex/chromeos.fmd:
https://review.coreboot.org/c/coreboot/+/74229/comment/2f87bbbe_13a7d393
PS1, Line 7: 7M
> > Changing 7092K to 7M is cosmetic, isn’t it?
>
> @Paul, you have to understand every bytes are meaningful here. I can't just drop 92K in one CL without adding those 92K to any other region.
@Paul, i'm marking this done. please let me know otherwise
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Hello build bot (Jenkins), Tarun Tuli, Kapil Porwal,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74229
to look at the new patch set (#5).
Change subject: mb/google/rex: Update Flash Layout to fit WP_RO within 4MB
......................................................................
mb/google/rex: Update Flash Layout to fit WP_RO within 4MB
This patch updates the Rex flash layout to optimize WP_RO to 4MB.
The idea is to create more space inside FW_RW_A/B to accommodate
multiple blobs to boot google/rex with different Intel MTL SoC stepping.
Changes for chromeos.fmd:
SI_BIOS:
RW_SECTION_A/B: Reduce to 7MB.
RW_LEGACY: Reduce to 1MB.
RW_MISC: Increased to 1MB.
RW_UNUSED: 3MB (reserved)
WP_RO: Reduce to 4MB
Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the
SPI Flash.
BUG=b:277143384
TEST=Able to build and boot google/rex with FSP release and debug image.
Change-Id: Iccf83b7bb66d0d5503e0ff9e9a819051296c6724
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/rex/chromeos.fmd
1 file changed, 52 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/74229/5
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