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Change subject: soc/amd/common/blk/pcie: Program LTR max latencies
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Patch Set 3:
(1 comment)
File src/soc/amd/common/block/pci/pcie_gpp.c:
https://review.coreboot.org/c/coreboot/+/74288/comment/4fe9f318_ca423a6e
PS1, Line 51: PCIE_LTR_MAX_LATENCY_1047US
> Let's add a Kconfig when things begin to deviate. Until then YAGNI.
Ack
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Change subject: soc/amd/common/blk/pcie: Program LTR max latencies
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File src/soc/amd/common/block/pci/pcie_gpp.c:
https://review.coreboot.org/c/coreboot/+/74288/comment/623ca215_317609a2
PS1, Line 51: PCIE_LTR_MAX_LATENCY_1047US
> or, the SoC can override the common value at the SoC level, just like Intel is doing :)
Let's add a Kconfig when things begin to deviate. Until then YAGNI.
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