coreboot-gerrit April 2023

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[S] Change in coreboot[master]: mb/google/sarien: Set touchpad/screen IRQs to LEVEL vs EDGE
by Matt DeVillier (Code Review) 10 Apr '23

10 Apr '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74238 ) Change subject: mb/google/sarien: Set touchpad/screen IRQs to LEVEL vs EDGE ...................................................................... mb/google/sarien: Set touchpad/screen IRQs to LEVEL vs EDGE Ensure the GPIOs themselves are configured as level triggered, as well as the devicetree entiures. I2C-HID spec requires LEVEL trigger, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE trigger. TEST=tested with rest of patch train Change-Id: I4fba55c938f401876798c2b32c5922523f32180f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74238 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/sarien/variants/sarien/gpio.c 4 files changed, 25 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index ee7fa60..52c37df 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -324,7 +324,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" register "detect" = "1" device i2c 2c on end end diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index 45aed5f..3051e3a 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -39,7 +39,7 @@ /* CORE_VID1 */ /* VRALERT# */ PAD_NC(GPP_B2, NONE), /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ + LEVEL, INVERT), /* TOUCHPAD_INTR# */ /* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ /* LAN_CLKREQ_CPU_N */ /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index f01950e..1e9d321 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -338,7 +338,7 @@ chip drivers/i2c/generic register "hid" = ""MLFS0000"" register "desc" = ""Melfas Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" register "probed" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" register "reset_delay_ms" = "10" @@ -354,7 +354,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" register "detect" = "1" device i2c 2c on end end diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index 5eb5607..d02d69b 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -34,7 +34,7 @@ /* CORE_VID1 */ /* VRALERT# */ PAD_NC(GPP_B2, NONE), /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ + LEVEL, INVERT), /* TOUCHPAD_INTR# */ /* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLKREQ_PCIE#0 */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* CLKREQ_PCIE#1 */ @@ -81,7 +81,7 @@ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ /* UART2_RTS# */ PAD_NC(GPP_C22, NONE), /* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* TS_INT# */ + LEVEL, INVERT), /* TS_INT# */ /* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST, EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74238 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fba55c938f401876798c2b32c5922523f32180f Gerrit-Change-Number: 74238 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/sarien: Implement touchscreen power sequencing
by Matt DeVillier (Code Review) 10 Apr '23

10 Apr '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74237 ) Change subject: mb/google/sarien: Implement touchscreen power sequencing ...................................................................... mb/google/sarien: Implement touchscreen power sequencing For touchscreens on sarien, drive the enable GPIO high starting in romstage while holding in reset, then disable the reset GPIO in ramstage. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). BUG=b:121309055 TEST=tested with rest of patch train Change-Id: I3ce7bfc0fa4c03c0bb96bebaa3c3d256f886ecc4 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74237 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/sarien/gpio.c 2 files changed, 38 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index 63df675..45aed5f 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -242,6 +242,12 @@ /* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ }; +static const struct pad_config romstage_gpio_table[] = { + /* Enable touchscreen, hold in reset */ + PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ + PAD_CFG_GPO(GPP_E7, 0, DEEP), /* TOUCH_SCREEN_PD# */ +}; + const struct pad_config *variant_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); @@ -256,8 +262,8 @@ const struct pad_config *variant_romstage_gpio_table(size_t *num) { - *num = 0; - return NULL; + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; } static const struct cros_gpio cros_gpios[] = { diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index f9797d3..5eb5607 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -230,6 +230,12 @@ /* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ }; +static const struct pad_config romstage_gpio_table[] = { + /* Enable touchscreen, hold in reset */ + PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ + PAD_CFG_GPO(GPP_E7, 0, DEEP), /* TOUCH_SCREEN_PD# */ +}; + const struct pad_config *variant_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); @@ -244,8 +250,8 @@ const struct pad_config *variant_romstage_gpio_table(size_t *num) { - *num = 0; - return NULL; + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; } static const struct cros_gpio cros_gpios[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/74237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ce7bfc0fa4c03c0bb96bebaa3c3d256f886ecc4 Gerrit-Change-Number: 74237 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/sarien: Add method to set GPIOs in romstage
by Matt DeVillier (Code Review) 10 Apr '23

10 Apr '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74236 ) Change subject: mb/google/sarien: Add method to set GPIOs in romstage ...................................................................... mb/google/sarien: Add method to set GPIOs in romstage Add method variant_romstage_gpio_table() with empty implementation to be used in a subsequent commit for touchscreen power sequencing. Call method in romstage to program any GPIOs that may need to be set. TEST=tested with rest of patch train Change-Id: I11b72a10a4a105385fbcf1d795c020708a7a90d9 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74236 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/sarien/romstage.c M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h M src/mainboard/google/sarien/variants/sarien/gpio.c M src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h 5 files changed, 40 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/sarien/romstage.c b/src/mainboard/google/sarien/romstage.c index bc0a799..8045112 100644 --- a/src/mainboard/google/sarien/romstage.c +++ b/src/mainboard/google/sarien/romstage.c @@ -3,6 +3,7 @@ #include <ec/google/wilco/romstage.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> +#include <variant/gpio.h> static const struct cnl_mb_cfg memcfg = { /* Access memory info through SMBUS. */ @@ -44,7 +45,13 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { + const struct pad_config *pads; + size_t pads_num; + wilco_ec_romstage_init(); cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); + + pads = variant_romstage_gpio_table(&pads_num); + gpio_configure_pads(pads, pads_num); } diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index fbaeb39..63df675 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -254,6 +254,12 @@ return early_gpio_table; } +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h b/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h index f56059c..0472f60 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h @@ -14,5 +14,6 @@ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); +const struct pad_config *variant_romstage_gpio_table(size_t *num); #endif diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index 7f226e4..f9797d3 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -242,6 +242,12 @@ return early_gpio_table; } +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h b/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h index f56059c..0472f60 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h @@ -14,5 +14,6 @@ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); +const struct pad_config *variant_romstage_gpio_table(size_t *num); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/74236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11b72a10a4a105385fbcf1d795c020708a7a90d9 Gerrit-Change-Number: 74236 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/brya: Compile gpio.c in SMM when needed
by Matt DeVillier (Code Review) 10 Apr '23

10 Apr '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74233 ) Change subject: mb/google/brya: Compile gpio.c in SMM when needed ...................................................................... mb/google/brya: Compile gpio.c in SMM when needed Without gpio.c compiled in, SMMSTORE will fail to initialize and hang. Add a conditional inclusion so gpio.c is compiled in SMM when SMMSTORE is selected. TEST=build/boot google/banshee with SMMSTORE support enabled Change-Id: If049cba98f13f060807058029306dcad2ada2d49 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74233 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc M src/mainboard/google/brya/variants/baseboard/brya/Makefile.inc M src/mainboard/google/brya/variants/baseboard/nissa/Makefile.inc 3 files changed, 25 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tarun Tuli: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc index 8a4b2ac..53aaa41 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc +++ b/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc @@ -5,3 +5,5 @@ ramstage-y += gpio.c ramstage-y += ramstage.c + +smm-$(CONFIG_SMMSTORE) += gpio.c diff --git a/src/mainboard/google/brya/variants/baseboard/brya/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/brya/Makefile.inc index 8a4b2ac..53aaa41 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/Makefile.inc +++ b/src/mainboard/google/brya/variants/baseboard/brya/Makefile.inc @@ -5,3 +5,5 @@ ramstage-y += gpio.c ramstage-y += ramstage.c + +smm-$(CONFIG_SMMSTORE) += gpio.c diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.inc index 8a4b2ac..53aaa41 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.inc +++ b/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.inc @@ -5,3 +5,5 @@ ramstage-y += gpio.c ramstage-y += ramstage.c + +smm-$(CONFIG_SMMSTORE) += gpio.c -- To view, visit https://review.coreboot.org/c/coreboot/+/74233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If049cba98f13f060807058029306dcad2ada2d49 Gerrit-Change-Number: 74233 Gerrit-PatchSet: 5 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/poppy/var/nami: Fix stylus runtime detection
by Matt DeVillier (Code Review) 10 Apr '23

10 Apr '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74234 ) Change subject: mb/google/poppy/var/nami: Fix stylus runtime detection ...................................................................... mb/google/poppy/var/nami: Fix stylus runtime detection Stylus reset GPIO needs to be held low in romstage, released in ramstage for runtime i2c detection to pick it up. TEST=build/boot AKALI360 variant, verify stylus detected in cbmem, functional in OS. Change-Id: I2e7f2a28f6b3a71b0c8fc367168cffbe3f064663 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74234 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/mainboard/google/poppy/variants/nami/gpio.c 1 file changed, 23 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Sean Rhodes: Looks good to me, approved diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c index 8df93f2..68f0f5b 100644 --- a/src/mainboard/google/poppy/variants/nami/gpio.c +++ b/src/mainboard/google/poppy/variants/nami/gpio.c @@ -153,7 +153,7 @@ /* D2 : SPI1_MISO ==> PEN_PDCT# */ PAD_CFG_GPI_APIC_HIGH(GPP_D2, NONE, PLTRST), /* D3 : SPI1_MOSI ==> PEN_RST# */ - PAD_CFG_GPO(GPP_D3, 0, DEEP), + PAD_CFG_GPO(GPP_D3, 1, DEEP), /* D4 : FASHTRIG ==> NC */ PAD_NC(GPP_D4, NONE), /* D5 : ISH_I2C0_SDA ==> NC */ @@ -486,6 +486,9 @@ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* B3 : CPU_GP2 ==> TOUCHSCREEN_RST# */ PAD_CFG_GPO(GPP_B3, 0, DEEP), + /* D3 : SPI1_MOSI ==> PEN_RST# */ + PAD_CFG_GPO(GPP_D3, 0, DEEP), + }; const struct pad_config *variant_romstage_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/74234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e7f2a28f6b3a71b0c8fc367168cffbe3f064663 Gerrit-Change-Number: 74234 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/fizz/var/fizz: update VBT
by Matt DeVillier (Code Review) 10 Apr '23

10 Apr '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74235 ) Change subject: mb/google/fizz/var/fizz: update VBT ...................................................................... mb/google/fizz/var/fizz: update VBT Deselect the 'fixed resolution at boot' and 'eFP attached' options via the Windows BMP tool. Fixes HDMI audio output under Windows 10/11. TEST=build/boot Win 11 on Fizz, verify HDMI audio now functional. Change-Id: Iecede735bc1266af837e791e6c024aec2f9a8a80 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74235 Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/fizz/variants/fizz/data.vbt 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sean Rhodes: Looks good to me, approved diff --git a/src/mainboard/google/fizz/variants/fizz/data.vbt b/src/mainboard/google/fizz/variants/fizz/data.vbt index dbbf475..6679742 100644 --- a/src/mainboard/google/fizz/variants/fizz/data.vbt +++ b/src/mainboard/google/fizz/variants/fizz/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/74235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecede735bc1266af837e791e6c024aec2f9a8a80 Gerrit-Change-Number: 74235 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: ACPI: Add helper for MADT LAPICs
by Sridhar Siricilla (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Lance Zhao, Jonathan Zhang, Johnny Lin, Tim Wawrzynczak, Christian Walter, Arthur Heymans, Ronak Kanabar, Kyösti Mälkki, Tim Chu. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74312 ) Change subject: ACPI: Add helper for MADT LAPICs ...................................................................... Patch Set 2: (1 comment) File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/74312/comment/cafe7b6f_2481f586 PS2, Line 150: 0xff > nit: is this worth a `#define` for, e.g. […] Good to see you back :) -- To view, visit https://review.coreboot.org/c/coreboot/+/74312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I592c69e0f52687924fe41189b082c86913999136 Gerrit-Change-Number: 74312 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 10 Apr 2023 15:03:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: sb,soc/amd,intel: Add and use ACPI_COMMON_MADT_LAPIC
by Tim Wawrzynczak (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Lance Zhao, Jason Glenesk, Raul Rangel, Matt DeVillier, Kyösti Mälkki, Fred Reitberger, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74316 ) Change subject: sb,soc/amd,intel: Add and use ACPI_COMMON_MADT_LAPIC ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74316/comment/878a594f_e0c195b7 PS1, Line 13: aopen/dxplplusu, emulation/qemu-i440fx,qemu-q35 why are these excluded? -- To view, visit https://review.coreboot.org/c/coreboot/+/74316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f8d7ee9891553742d73a92b55a87c04fa95a132 Gerrit-Change-Number: 74316 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 10 Apr 2023 14:48:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/common/blk/pcie: Program LTR max latencies
by Matt DeVillier (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Eric Lai, Martin Roth, Fred Reitberger, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74288 ) Change subject: soc/amd/common/blk/pcie: Program LTR max latencies ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/common/block/pci/pcie_gpp.c: https://review.coreboot.org/c/coreboot/+/74288/comment/d6f03232_5b3ddc86 PS1, Line 51: PCIE_LTR_MAX_LATENCY_1047US > IMHO Kconfig provides the flexibility for future change. But I am fine either way. or, the SoC can override the common value at the SoC level, just like Intel is doing :) -- To view, visit https://review.coreboot.org/c/coreboot/+/74288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf188e69cf5676be870873c56d175423d16704b4 Gerrit-Change-Number: 74288 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 10 Apr 2023 14:48:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: binaryPI: Use common code for LAPIC NMIs
by Tim Wawrzynczak (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Lance Zhao, Kyösti Mälkki, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74310 ) Change subject: binaryPI: Use common code for LAPIC NMIs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a39f355733d10ecd43a1da541ab2e66ba13db15 Gerrit-Change-Number: 74310 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 10 Apr 2023 14:47:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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