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Hello build bot (Jenkins), Tarun Tuli, Subrata Banik,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/: Store CSE firmware version into cbmem table
......................................................................
soc/intel/: Store CSE firmware version into cbmem table
The patch implements an API that stores the CSE firmware version in the
CBMEM table. The API will be called either from RAMSTAGE or ROMSTAGE
based on underlying platform.
BUG=b:273661726
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8
---
M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
M src/soc/intel/alderlake/romstage/romstage.c
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
4 files changed, 62 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/74256/6
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Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74288 )
Change subject: soc/amd/common/blk/pcie: Program LTR max latencies
......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/common/block/pci/pcie_gpp.c:
https://review.coreboot.org/c/coreboot/+/74288/comment/86257bf2_7896463d
PS1, Line 51: PCIE_LTR_MAX_LATENCY_1047US
> Why I ask is Intel have different requirement per CPU. https://review.coreboot. […]
Intel uses the same value for all 6th-13th gen SoCs; Meteorlake is the first to deviate from that. Looking at AMD's main AGESA trunk, the value is unchanged since first commit.
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Attention is currently required from: Dinesh Gehlot, Kapil Porwal.
Hello build bot (Jenkins), Subrata Banik, Kangheui Won, Kapil Porwal,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#6).
Change subject: soc/intel/cmd/block/cse: Add config option for storing fw version info
......................................................................
soc/intel/cmd/block/cse: Add config option for storing fw version info
This patch adds a configuration option,
'SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION', which enables the storage
of firmware version information in CBMEM memory. This information can be
used to identify the firmware version that is currently installed on the
system. The option depends on the `DRIVERS_INTEL_ISH` option.
BUG=b:273661726
Test=None
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: I78fef45fd2940536b3e91cfd4d184b7635238499
---
M src/soc/intel/common/block/cse/Kconfig
1 file changed, 27 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/74255/6
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Hello build bot (Jenkins), SRIDHAR SIRICILLA, Subrata Banik, Kangheui Won, Haribalaraman Ramasubramanian, Rizwan Qureshi, Reka Norman, Kapil Porwal, Sridhar Siricilla, Meera Ravindranath,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74005
to look at the new patch set (#26).
Change subject: soc/intel/cmd/block: Implement an API to get firmware partition details
......................................................................
soc/intel/cmd/block: Implement an API to get firmware partition details
This patch retrieves details of a specified firmware FPT partition. The
information retrieved includes the current firmware version and other
information about the FPT partition. The patch communicates with the ME
using the HECI command to acquire this information.
BUG=b:273661726
Test=Verified the changes for ISH partition on nissa board.
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 108 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/74005/26
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Change subject: mb/google/skyrim: Enable UPD usb3_port_force_gen1 for Markarth
......................................................................
Patch Set 2: Code-Review+1
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Bharath N has posted comments on this change. ( https://review.coreboot.org/c/qc_blobs/+/73955 )
Change subject: sc7180/qtiseclib: Update qtiseclib blobs binaries and release notes from 50 to 69
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/qc_blobs/+/73955/comment/d0b5aafa_355b1097
PS1, Line 9: TEST=Validated on qualcomm sc7180 development board
> Are there boot time changes?
there are no boot time changes, mostly sc7280 changes are included in #54 to #69.
File sc7180/qtiseclib/Release_Notes.txt:
https://review.coreboot.org/c/qc_blobs/+/73955/comment/4e7db483_50212ac9
PS1, Line 5: Version : 00069
> The last release we shipped internally contains manifest version 00054. […]
All recent changes up to #68 are static analysis, version #69 is related to longsys device stability issue.
https://review.coreboot.org/c/qc_blobs/+/73955/comment/379fa131_a4315d06
PS1, Line 14: * NOC error scripts
> What does NOC mean?
NoC is network on chip, mostly bus configuration for different sub systems on soc
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Change subject: mb/google/rex: Update Flash Layout to fit WP_RO within 4MB
......................................................................
Patch Set 4: Code-Review+2
(2 comments)
Patchset:
PS4:
> yes, the build fails if I enable fwconsole.
Marking it as "Resolved" since fwconsole is not a default option.
PS4:
These changes are working fine. I have also verified MRC fastboot.
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