coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

1 participants
5761 discussions

[M] Change in coreboot[master]: soc/intel: Introduce ioapic_get_sci_pin()
by Kyösti Mälkki (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74326 ) Change subject: soc/intel: Introduce ioapic_get_sci_pin() ...................................................................... soc/intel: Introduce ioapic_get_sci_pin() According to ACPI Release 6.5 systems supporting PIC (i8259) interrupt mechanism need to report IRQ vector for the SCI_INT field. In PIC mode only IRQ0..15 are allowed hardware vectors. This change should cover section 5.2.9 to not pass SCI_INT larger than IRQ15. Section 5.2.15.5 needs follow-up work. It appears touched platforms currently program SCI as IRQ9. Change-Id: I723c207f1dcbba5e6fc0452fe1dbd087fad290ee Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/acpi.c M src/arch/x86/include/arch/ioapic.h M src/include/acpi/acpi.h M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/fadt.c M src/soc/intel/baytrail/include/soc/acpi.h M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/fadt.c M src/soc/intel/braswell/include/soc/acpi.h M src/soc/intel/common/block/acpi/acpi.c 10 files changed, 102 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/74326/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 37eb4fe..04e8349 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -206,6 +206,24 @@ } #endif +u16 acpi_sci_int(void) +{ +#if ENV_X86 + u8 gsi, irq, flags; + + ioapic_get_sci_pin(&gsi, &irq, &flags); + + /* ACPI Release 6.5, 5.2.9 and 5.2.15.5. */ + if (!CONFIG(ACPI_HAVE_PCAT_8259)) + return gsi; + + assert(irq < 16); + return irq; +#else + return 0; +#endif +} + int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, u8 bus, u8 source, u32 gsirq, u16 flags) { diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index a91ac14..84852e0 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -23,6 +23,8 @@ void register_new_ioapic_gsi0(void *ioapic_base); void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb); + +void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags); #endif #endif diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 77f73ae..5e03f70 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1349,6 +1349,8 @@ unsigned long acpi_create_madt_lapic_nmis(unsigned long current); +u16 acpi_sci_int(void); + int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic); int acpi_create_srat_x2apic(acpi_srat_x2apic_t *x2apic, u32 node, u32 apic); int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index c6b5a18..4a08d6c 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -10,7 +10,6 @@ #include <cpu/x86/msr.h> #include <cpu/intel/turbo.h> -#include <soc/acpi.h> #include <soc/iomap.h> #include <soc/irq.h> #include <soc/msr.h> @@ -52,14 +51,21 @@ } }; -int acpi_sci_irq(void) +static u8 soc_madt_sci_irq_polarity(u8 sci_irq) +{ + if (sci_irq >= 20) + return MP_IRQ_POLARITY_LOW; + else + return MP_IRQ_POLARITY_HIGH; +} + +#define ACPI_SCI_IRQ 9 + +void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) { u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); + int sci_irq = ACPI_SCI_IRQ; int scis; - static int sci_irq; - - if (sci_irq) - return sci_irq; /* Determine how SCI is routed. */ scis = read32(actl) & SCIS_MASK; @@ -76,13 +82,15 @@ sci_irq = scis - SCIS_IRQ20 + 20; break; default: - printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); - sci_irq = 9; + printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ%d.\n", sci_irq); break; } - printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); - return sci_irq; + *gsi = sci_irq; + *irq = (sci_irq < 16) ? sci_irq : ACPI_SCI_IRQ; + *flags = MP_IRQ_TRIGGER_LEVEL | soc_madt_sci_irq_polarity(sci_irq); + + printk(BIOS_DEBUG, "SCI is IRQ %d, GSI %d\n", *irq, *gsi); } static acpi_tstate_t soc_tss_table[] = { @@ -278,21 +286,17 @@ static unsigned long acpi_madt_irq_overrides(unsigned long current) { - int sci_irq = acpi_sci_irq(); + u8 gsi, irq, flags; acpi_madt_irqoverride_t *irqovr; - uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL; + + ioapic_get_sci_pin(&gsi, &irq, &flags); /* INT_SRC_OVR */ irqovr = (void *)current; current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); - if (sci_irq >= 20) - sci_flags |= MP_IRQ_POLARITY_LOW; - else - sci_flags |= MP_IRQ_POLARITY_HIGH; - irqovr = (void *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, sci_flags); + current += acpi_create_madt_irqoverride(irqovr, 0, irq, gsi, flags); return current; } diff --git a/src/soc/intel/baytrail/fadt.c b/src/soc/intel/baytrail/fadt.c index 64154db..a76d161 100644 --- a/src/soc/intel/baytrail/fadt.c +++ b/src/soc/intel/baytrail/fadt.c @@ -11,7 +11,7 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - fadt->sci_int = acpi_sci_irq(); + fadt->sci_int = acpi_sci_int(); if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; diff --git a/src/soc/intel/baytrail/include/soc/acpi.h b/src/soc/intel/baytrail/include/soc/acpi.h index b747db7..db07de1 100644 --- a/src/soc/intel/baytrail/include/soc/acpi.h +++ b/src/soc/intel/baytrail/include/soc/acpi.h @@ -5,6 +5,4 @@ #include <acpi/acpi.h> -int acpi_sci_irq(void); - #endif /* _BAYTRAIL_ACPI_H_ */ diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 6ea1039..6de076b 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -81,14 +81,21 @@ gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN; } -int acpi_sci_irq(void) +static u8 soc_madt_sci_irq_polarity(u8 sci_irq) +{ + if (sci_irq >= 20) + return MP_IRQ_POLARITY_LOW; + else + return MP_IRQ_POLARITY_HIGH; +} + +#define ACPI_SCI_IRQ 9 + +void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) { u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); + int sci_irq = ACPI_SCI_IRQ; int scis; - static int sci_irq; - - if (sci_irq) - return sci_irq; /* Determine how SCI is routed. */ scis = read32(actl) & SCIS_MASK; @@ -105,13 +112,15 @@ sci_irq = scis - SCIS_IRQ20 + 20; break; default: - printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); - sci_irq = 9; + printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ%d.\n", sci_irq); break; } - printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); - return sci_irq; + *gsi = sci_irq; + *irq = (sci_irq < 16) ? sci_irq : ACPI_SCI_IRQ; + *flags = MP_IRQ_TRIGGER_LEVEL | soc_madt_sci_irq_polarity(sci_irq); + + printk(BIOS_DEBUG, "SCI is IRQ %d, GSI %d\n", *irq, *gsi); } static acpi_tstate_t soc_tss_table[] = { @@ -307,21 +316,17 @@ static unsigned long acpi_madt_irq_overrides(unsigned long current) { - int sci_irq = acpi_sci_irq(); + u8 gsi, irq, flags; acpi_madt_irqoverride_t *irqovr; - uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL; + + ioapic_get_sci_pin(&gsi, &irq, &flags); /* INT_SRC_OVR */ irqovr = (void *)current; current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); - if (sci_irq >= 20) - sci_flags |= MP_IRQ_POLARITY_LOW; - else - sci_flags |= MP_IRQ_POLARITY_HIGH; - irqovr = (void *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, sci_flags); + current += acpi_create_madt_irqoverride(irqovr, 0, irq, gsi, flags); return current; } diff --git a/src/soc/intel/braswell/fadt.c b/src/soc/intel/braswell/fadt.c index 64154db..a76d161 100644 --- a/src/soc/intel/braswell/fadt.c +++ b/src/soc/intel/braswell/fadt.c @@ -11,7 +11,7 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - fadt->sci_int = acpi_sci_irq(); + fadt->sci_int = acpi_sci_int(); if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h index ccb48eb..fa4c804 100644 --- a/src/soc/intel/braswell/include/soc/acpi.h +++ b/src/soc/intel/braswell/include/soc/acpi.h @@ -5,7 +5,6 @@ #include <acpi/acpi.h> -int acpi_sci_irq(void); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); unsigned long southcluster_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 50b4573..8f10f9a 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -24,9 +24,11 @@ #define CPUID_6_EAX_ISST (1 << 7) -static int acpi_sci_irq(void) +#define ACPI_SCI_IRQ 9 + +void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) { - int sci_irq = 9; + int sci_irq = ACPI_SCI_IRQ; uint32_t scis; scis = soc_read_sci_irq_select(); @@ -47,28 +49,28 @@ sci_irq = scis - SCIS_IRQ20 + 20; break; default: - printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); - sci_irq = 9; + printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ%d.\n", sci_irq); break; } - printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); - return sci_irq; + *gsi = sci_irq; + *irq = (sci_irq < 16) ? sci_irq : ACPI_SCI_IRQ; + *flags = MP_IRQ_TRIGGER_LEVEL | soc_madt_sci_irq_polarity(sci_irq); + + printk(BIOS_DEBUG, "SCI is IRQ %d, GSI %d\n", *irq, *gsi); } static unsigned long acpi_madt_irq_overrides(unsigned long current) { - int sci = acpi_sci_irq(); - uint16_t flags = MP_IRQ_TRIGGER_LEVEL; + u8 gsi, irq, flags; + + ioapic_get_sci_pin(&gsi, &irq, &flags); /* INT_SRC_OVR */ current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); - flags |= soc_madt_sci_irq_polarity(sci); - /* SCI */ - current += - acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags); + current += acpi_create_madt_irqoverride((void *)current, 0, irq, gsi, flags); return current; } @@ -102,7 +104,7 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - fadt->sci_int = acpi_sci_irq(); + fadt->sci_int = acpi_sci_int(); if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; -- To view, visit https://review.coreboot.org/c/coreboot/+/74326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I723c207f1dcbba5e6fc0452fe1dbd087fad290ee Gerrit-Change-Number: 74326 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: soc/intel/baytrail: Move a function inside a file
by Kyösti Mälkki (Code Review) 10 Apr '23

10 Apr '23

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74325 ) Change subject: soc/intel/baytrail: Move a function inside a file ...................................................................... soc/intel/baytrail: Move a function inside a file This avoids unnecessary forward declaration of another statically defined function. Change-Id: Id362e023358054df2c4511fd108c313da868306d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/include/soc/acpi.h 2 files changed, 24 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/74325/1 diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 4d5b5c2..c6b5a18 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -85,16 +85,6 @@ return sci_irq; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* IOAPIC */ - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - - current = acpi_madt_irq_overrides(current); - - return current; -} - static acpi_tstate_t soc_tss_table[] = { { 100, 1000, 0, 0x00, 0 }, { 88, 875, 0, 0x1e, 0 }, @@ -286,7 +276,7 @@ acpigen_write_processor_cnot(pattrs->num_cpus); } -unsigned long acpi_madt_irq_overrides(unsigned long current) +static unsigned long acpi_madt_irq_overrides(unsigned long current) { int sci_irq = acpi_sci_irq(); acpi_madt_irqoverride_t *irqovr; @@ -306,3 +296,13 @@ return current; } + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* IOAPIC */ + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); + + current = acpi_madt_irq_overrides(current); + + return current; +} diff --git a/src/soc/intel/baytrail/include/soc/acpi.h b/src/soc/intel/baytrail/include/soc/acpi.h index d629b24..b747db7 100644 --- a/src/soc/intel/baytrail/include/soc/acpi.h +++ b/src/soc/intel/baytrail/include/soc/acpi.h @@ -6,6 +6,5 @@ #include <acpi/acpi.h> int acpi_sci_irq(void); -unsigned long acpi_madt_irq_overrides(unsigned long current); #endif /* _BAYTRAIL_ACPI_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id362e023358054df2c4511fd108c313da868306d Gerrit-Change-Number: 74325 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: sb,soc/amd,intel: Add and use ACPI_COMMON_MADT_LAPIC
by Kyösti Mälkki (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Lance Zhao, Jason Glenesk, Raul Rangel, Matt DeVillier, Kyösti Mälkki, Fred Reitberger, Felix Held. Hello Lance Zhao, build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Tim Wawrzynczak, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74316 to look at the new patch set (#2). Change subject: sb,soc/amd,intel: Add and use ACPI_COMMON_MADT_LAPIC ...................................................................... sb,soc/amd,intel: Add and use ACPI_COMMON_MADT_LAPIC Boards with SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID have special handling for the time being. Change of aopen/dxplplusu is coupled with sb/intel/i82801dx. Change of emulation/qemu-i440fx is coupled with intel/i82371eb. Change-Id: I1f8d7ee9891553742d73a92b55a87c04fa95a132 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/Kconfig M src/acpi/acpi.c M src/mainboard/aopen/dxplplusu/acpi_tables.c M src/mainboard/emulation/qemu-i440fx/acpi_tables.c M src/northbridge/amd/pi/00730F01/acpi_tables.c M src/soc/amd/cezanne/acpi.c M src/soc/amd/common/block/acpi/Kconfig M src/soc/amd/glinda/acpi.c M src/soc/amd/mendocino/acpi.c M src/soc/amd/phoenix/acpi.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/acpi.c M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/pch/Kconfig M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi.c M src/southbridge/amd/pi/hudson/Kconfig M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/common/madt.c M src/southbridge/intel/i82371eb/Kconfig M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801ix/madt.c M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/ibexpeak/madt.c M src/southbridge/intel/lynxpoint/Kconfig 33 files changed, 37 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/74316/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f8d7ee9891553742d73a92b55a87c04fa95a132 Gerrit-Change-Number: 74316 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: ACPI: Add helper for MADT LAPICs
by Kyösti Mälkki (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Lance Zhao, Jonathan Zhang, Johnny Lin, Tim Wawrzynczak, Christian Walter, Arthur Heymans, Ronak Kanabar, Kyösti Mälkki, Tim Chu. Hello Lance Zhao, build bot (Jenkins), Jonathan Zhang, Johnny Lin, Tim Wawrzynczak, Christian Walter, Sridhar Siricilla, Arthur Heymans, Ronak Kanabar, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74312 to look at the new patch set (#3). Change subject: ACPI: Add helper for MADT LAPICs ...................................................................... ACPI: Add helper for MADT LAPICs This avoids some code duplication related to X2APIC mode. Change-Id: I592c69e0f52687924fe41189b082c86913999136 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/acpi.c M src/include/acpi/acpi.h M src/soc/intel/common/block/acpi/cpu_hybrid.c M src/soc/intel/xeon_sp/spr/soc_acpi.c 4 files changed, 35 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/74312/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I592c69e0f52687924fe41189b082c86913999136 Gerrit-Change-Number: 74312 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: mb/google/myst: Enable gfx_hda
by Tim Van Patten (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Paul Menzel, Karthik Ramasubramanian, Mark Hasemeyer. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74278 ) Change subject: mb/google/myst: Enable gfx_hda ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58096f1408f66f968af1494e487cf2bfc43b9a0f Gerrit-Change-Number: 74278 Gerrit-PatchSet: 6 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Mon, 10 Apr 2023 17:38:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/myst: Enable mp2 device
by Tim Van Patten (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Raul Rangel, Jason Nien, Jon Murphy, Martin Roth, Karthik Ramasubramanian, Mark Hasemeyer. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74277 ) Change subject: mb/google/myst: Enable mp2 device ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21885c51ff08846b456675090946f381843ef5e6 Gerrit-Change-Number: 74277 Gerrit-PatchSet: 5 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Mon, 10 Apr 2023 17:37:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/myst: Enable variants for Myst
by Karthik Ramasubramanian (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Mark Hasemeyer. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74098 ) Change subject: mb/google/myst: Enable variants for Myst ...................................................................... Patch Set 17: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I688e9c2fdf203cecfd5f200dec6cde9dbc0a9aa7 Gerrit-Change-Number: 74098 Gerrit-PatchSet: 17 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Mon, 10 Apr 2023 17:27:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: rex: add variant gpio tables for variant creation
by Subrata Banik (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: YH Lin, Tarun Tuli, Kapil Porwal, Paul Fagerburg. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74257 ) Change subject: rex: add variant gpio tables for variant creation ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Ah I see. But I am not sure the codes generated by new_variants will support this scheme? > > +Paul for comment as well. > > Thanks. are you referring to https://review.coreboot.org/c/coreboot/+/71086 CL ? -- To view, visit https://review.coreboot.org/c/coreboot/+/74257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebc098f8d480ac3e1835b00861fd844d97f281a8 Gerrit-Change-Number: 74257 Gerrit-PatchSet: 1 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Comment-Date: Mon, 10 Apr 2023 17:20:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: YH Lin <yueherngl(a)google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: rex: add variant gpio tables for variant creation
by YH Lin (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Paul Fagerburg. YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74257 ) Change subject: rex: add variant gpio tables for variant creation ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > The implementation is little different in Rex in terms GPIO (compared to the Brya) […] Ah I see. But I am not sure the codes generated by new_variants will support this scheme? +Paul for comment as well. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/74257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebc098f8d480ac3e1835b00861fd844d97f281a8 Gerrit-Change-Number: 74257 Gerrit-PatchSet: 1 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Comment-Date: Mon, 10 Apr 2023 17:17:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/google/myst: Enable PCIe devices in devicetree
by Jon Murphy (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Raul Rangel, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74112 ) Change subject: mb/google/myst: Enable PCIe devices in devicetree ...................................................................... Patch Set 31: (1 comment) File src/mainboard/google/myst/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/74112/comment/8baad13c_fba5c1b5 PS31, Line 101: *dxio_descs = myst_phx_dxio_descriptors; : *dxio_num = ARRAY_SIZE(myst_phx_dxio_descriptors); : *ddi_descs = myst_phx_ddi_descriptors; : *ddi_num = ARRAY_SIZE(myst_phx_ddi_descriptors); > Are these values actually specific to Phoenix? […] I would expect them to keep working, but I think it's possible that there would be a delta. We could probably just make it myst and update as needed -- To view, visit https://review.coreboot.org/c/coreboot/+/74112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Gerrit-Change-Number: 74112 Gerrit-PatchSet: 31 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Mon, 10 Apr 2023 17:16:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2023