coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/myst: Disable keyboard reset pin
by Tim Van Patten (Code Review) 10 Apr '23

10 Apr '23

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[M] Change in coreboot[master]: mb/google/myst: Enable PCIe devices in devicetree
by Tim Van Patten (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Karthik Ramasubramanian, Mark Hasemeyer. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74112 ) Change subject: mb/google/myst: Enable PCIe devices in devicetree ...................................................................... Patch Set 31: (6 comments) File src/mainboard/google/myst/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/74112/comment/b002f3f3_fb00a5f2 PS31, Line 12: .start_logical_lane = 13, : .end_logical_lane = 13, https://ee-schematics.teams.x20web.corp.google.com/myst/myst/proto0/referen… > PCIe GPP 12 https://review.coreboot.org/c/coreboot/+/74112/comment/95b9e240_030a0189 PS31, Line 18: .link_aspm = ASPM_L1, : .link_aspm_L1_1 = true, : .link_aspm_L1_2 = true, Considering all of the trouble we've had with ASPM in the past, I would suggest disabling it for all of these and marking them with a TODO to re-enable it once we can boot/suspend/resume without issues. https://review.coreboot.org/c/coreboot/+/74112/comment/627951c9_d5cc8deb PS31, Line 44: GEN3 GEN1 https://review.coreboot.org/c/coreboot/+/74112/comment/fe75c5cb_197b6dcd PS31, Line 59: GEN3 GEN4 https://review.coreboot.org/c/coreboot/+/74112/comment/07b529f5_866c0a6c PS31, Line 101: *dxio_descs = myst_phx_dxio_descriptors; : *dxio_num = ARRAY_SIZE(myst_phx_dxio_descriptors); : *ddi_descs = myst_phx_ddi_descriptors; : *ddi_num = ARRAY_SIZE(myst_phx_ddi_descriptors); Are these values actually specific to Phoenix? If so, can we validate the SOC we're running on before applying them, and add a TODO for HP1/2? Otherwise, this feels like a bit of a silent trap that's easy to be missed when trying to bring up the new SOCs. However, if they're expected to keep working, the `phx` should be dropped from the name to avoid confusion. File src/mainboard/google/myst/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/74112/comment/c0b32723_ce38a219 PS8, Line 52: device ref gpp_bridge_2_4 on end # NVMe > My lane mapping in port_descriptors was incorrect, but these are notional naming conventions and can […] We need to make sure the naming is updated in depthcharge also: https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/… -- To view, visit https://review.coreboot.org/c/coreboot/+/74112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Gerrit-Change-Number: 74112 Gerrit-PatchSet: 31 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Mon, 10 Apr 2023 17:12:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Comment-In-Reply-To: Mark Hasemeyer <markhas(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/cmd/block: Implement an API to get firmware partition details
by Dinesh Gehlot (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Subrata Banik, Haribalaraman Ramasubramanian, Rizwan Qureshi, Reka Norman, Kapil Porwal, Sridhar Siricilla. Dinesh Gehlot has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74005 ) Change subject: soc/intel/cmd/block: Implement an API to get firmware partition details ...................................................................... Patch Set 27: (2 comments) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/74005/comment/1dabf4d9_ace16120 PS26, Line 1224: partitionId > > nit:camelcase needs to be avoided […] Ack https://review.coreboot.org/c/coreboot/+/74005/comment/31d79fdb_93dcf422 PS26, Line 1240: if (cse_is_hfs1_com_soft_temp_disable()) { : printk(BIOS_ERR, "HECI: Prerequisites not met for fw partition request\n"); : return false; : } : : if (!cse_is_hfs1_cws_normal() || !cse_is_hfs1_com_normal()) { : printk(BIOS_ERR, "HECI: Prerequisites not met for fw partition request\n"); : return false; : } > Can you combine these 2 conditions? May be you can do through separate CL. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/74005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 Gerrit-Change-Number: 74005 Gerrit-PatchSet: 27 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Mon, 10 Apr 2023 17:11:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/cmd/block: Implement an API to get firmware partition details
by Dinesh Gehlot (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Haribalaraman Ramasubramanian, Dinesh Gehlot, Rizwan Qureshi, Reka Norman, Kapil Porwal, Sridhar Siricilla. Hello build bot (Jenkins), SRIDHAR SIRICILLA, Subrata Banik, Kangheui Won, Haribalaraman Ramasubramanian, Rizwan Qureshi, Reka Norman, Kapil Porwal, Sridhar Siricilla, Meera Ravindranath, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74005 to look at the new patch set (#27). Change subject: soc/intel/cmd/block: Implement an API to get firmware partition details ...................................................................... soc/intel/cmd/block: Implement an API to get firmware partition details This patch retrieves details of a specified firmware FPT partition. The information retrieved includes the current firmware version and other information about the FPT partition. The patch communicates with the ME using the HECI command to acquire this information. BUG=b:273661726 Test=Verified the changes for ISH partition on nissa board. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 104 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/74005/27 -- To view, visit https://review.coreboot.org/c/coreboot/+/74005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 Gerrit-Change-Number: 74005 Gerrit-PatchSet: 27 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/mtl/romstage: Insert EC boot timestamps
by Jay Patel (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Bora Guvendik, Hannah Williams, Tarun Tuli, Jamie Ryu, Subrata Banik, Wonkyu Kim, Paul Menzel, Kapil Porwal. Jay Patel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73191 ) Change subject: soc/intel/mtl/romstage: Insert EC boot timestamps ...................................................................... Patch Set 10: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/73191/comment/1416797c_a9b28798 PS4, Line 9: Calls the function to insert EC boot timestamps to the coreboot > can you add a sample snippet of cbmem -t output with these timestamps? (somewhere in the patch trai […] Added in the shared design doc mentioned in the bug. File src/soc/intel/meteorlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/73191/comment/3f226738_6e2d0379 PS3, Line 142: insert_ec_event_timestamps(); > the function computes -ve timestamps based on SOC timer. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/73191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebda928a31d55a081f68b9833b66f757a9cd9aa7 Gerrit-Change-Number: 73191 Gerrit-PatchSet: 10 Gerrit-Owner: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 10 Apr 2023 16:45:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tarun Tuli <taruntuli(a)google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jay Patel <jay2.patel(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mainboard/google/rex/Kconfig: Enable EC boot timestamps for mtl-rex
by Jay Patel (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Bora Guvendik, Hannah Williams, Tarun Tuli, Jamie Ryu, Subrata Banik, Wonkyu Kim, Paul Menzel, Kapil Porwal. Jay Patel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73192 ) Change subject: mainboard/google/rex/Kconfig: Enable EC boot timestamps for mtl-rex ...................................................................... Patch Set 10: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/73192/comment/2296a144_93edaaef PS6, Line 13: cbmem -t > please share the boot_perf revised numbers w/ and w/o ur cl. Attached on bug 271012752 -- To view, visit https://review.coreboot.org/c/coreboot/+/73192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0b773fb4c7abfcb3c3ab061d970327987536fb2 Gerrit-Change-Number: 73192 Gerrit-PatchSet: 10 Gerrit-Owner: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 10 Apr 2023 16:44:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/common/blk/pcie: Program LTR max latencies
by Martin Roth (Code Review) 10 Apr '23

10 Apr '23

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74288 ) Change subject: soc/amd/common/blk/pcie: Program LTR max latencies ...................................................................... soc/amd/common/blk/pcie: Program LTR max latencies PCIe bridges need to provide the LTR (latency tolerance reporting) maximum snoop/non-snoop values so that they are inherited by downstream PCIe devices which support and enable LTR. Without this, downstream devices cannot have LTR enabled, which is a requirement for supporting PCIe L1 substates. Enabling L1ss without LTR has unpredictable behavior, including some devices refusing to enter L1 low power modes at all. Program the max snoop/non-snoop latency values for all PCIe bridges using the same value used by AGESA/FSP, 1.049ms. BUG=b:265890321 TEST=build/boot google/skyrim (multiple variants, NVMe drives), ensure LTR is enabled, latency values are correctly set, and that device power draw at idle is in the expected range (<25 mW). Change-Id: Icf188e69cf5676be870873c56d175423d16704b4 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74288 Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/soc/amd/common/block/pci/pcie_gpp.c 1 file changed, 45 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/common/block/pci/pcie_gpp.c b/src/soc/amd/common/block/pci/pcie_gpp.c index 0ce3268..0f983d0 100644 --- a/src/soc/amd/common/block/pci/pcie_gpp.c +++ b/src/soc/amd/common/block/pci/pcie_gpp.c @@ -47,6 +47,20 @@ acpigen_pop_len(); /* Scope */ } +/* Latency tolerance reporting, max snoop/non-snoop latency value 1.049ms */ +#define PCIE_LTR_MAX_LATENCY_1049US 0x1001 + +static void pcie_get_ltr_max_latencies(u16 *max_snoop, u16 *max_nosnoop) +{ + *max_snoop = PCIE_LTR_MAX_LATENCY_1049US; + *max_nosnoop = PCIE_LTR_MAX_LATENCY_1049US; +} + +static struct pci_operations pcie_ops = { + .get_ltr_max_latencies = pcie_get_ltr_max_latencies, + .set_subsystem = pci_dev_set_subsystem, +}; + struct device_operations amd_internal_pcie_gpp_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, @@ -65,4 +79,5 @@ .reset_bus = pci_bus_reset, .acpi_name = pcie_gpp_acpi_name, .acpi_fill_ssdt = acpi_device_write_gpp_pci_dev, + .ops_pci = &pcie_ops, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/74288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf188e69cf5676be870873c56d175423d16704b4 Gerrit-Change-Number: 74288 Gerrit-PatchSet: 6 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/common/blk/pcie: Program LTR max latencies
by Martin Roth (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Eric Lai, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74288 ) Change subject: soc/amd/common/blk/pcie: Program LTR max latencies ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf188e69cf5676be870873c56d175423d16704b4 Gerrit-Change-Number: 74288 Gerrit-PatchSet: 5 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 10 Apr 2023 16:40:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/cmd/block: Implement an API to get firmware partition details
by Subrata Banik (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Haribalaraman Ramasubramanian, Dinesh Gehlot, Rizwan Qureshi, Reka Norman, Kapil Porwal, Sridhar Siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74005 ) Change subject: soc/intel/cmd/block: Implement an API to get firmware partition details ...................................................................... Patch Set 26: (1 comment) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/74005/comment/7e5688dc_e8a97350 PS26, Line 1224: partitionId > nit:camelcase needs to be avoided good catch -- To view, visit https://review.coreboot.org/c/coreboot/+/74005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 Gerrit-Change-Number: 74005 Gerrit-PatchSet: 26 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Mon, 10 Apr 2023 16:38:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix/Kconfig: Prevent changes to AMD_FWM_POSITION_INDEX
by Fred Reitberger (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Paul Menzel, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74249 ) Change subject: soc/amd/phoenix/Kconfig: Prevent changes to AMD_FWM_POSITION_INDEX ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/phoenix/Kconfig: https://review.coreboot.org/c/coreboot/+/74249/comment/f6b26fbe_54e89252 PS2, Line 310: Typically this is calculated by the ROM size, but there may : be situations where you want to put the firmware directory : table in a different location. : 0: 512 KB - 0xFFFA0000 : 1: 1 MB - 0xFFF20000 : 2: 2 MB - 0xFFE20000 : 3: 4 MB - 0xFFC20000 : 4: 8 MB - 0xFF820000 : 5: 16 MB - 0xFF020000 > This is the common help text for that option for other AMD SOCs. […] Looking at the google boards that override this, they do not use any help at all, so updated to follow that style. -- To view, visit https://review.coreboot.org/c/coreboot/+/74249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f720dbadf2d28a3c39daa4bd653a407be4893d0 Gerrit-Change-Number: 74249 Gerrit-PatchSet: 4 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 10 Apr 2023 16:38:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: comment

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