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Change subject: soc/intel/common: Fix acpigen use for processor Device
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74395/comment/4dc66d9a_6e818d3a
PS1, Line 8:
> It’s incorrect since the beginning, commit bd427803ab18 (soc/intel/common/block: Common ACPI)? […]
Both work. Sometimes nested acpigen calls get hard to read, so one may prefer to not use pop_len().
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Change subject: soc/intel/meteorlake: Add VPU into the DMAR SATC table
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/meteorlake/acpi.c:
https://review.coreboot.org/c/coreboot/+/74221/comment/c52d7177_25cec4d0
PS1, Line 273: acpi_create_dmar_ds_pci
> Could you please confirm that there are no errors seen when VPU is disabled with this CL?
I sync to ToT(VPU is disabled) and did not observe error with this CL.
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Change subject: vc/amd/fsp/phoenix/platform_descriptors: add PCIe gen 4 link speed
......................................................................
Patch Set 1: Code-Review+2
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Change subject: payloads/edk2: Remove ABOVE_4G_MEMORY option
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> Just FYI for your branch
dc5f2905ebfdf68ae28ce1081d435af0f8641dd9 is not part of the current default branch uefipayload_202207, so we'll want to bump that first before dropping this option
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Change subject: payloads/edk2: Remove ABOVE_4G_MEMORY option
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Just FYI for your branch
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Change subject: vc/amd/fsp/phoenix/platform_descriptors: add PCIe gen 4 link speed
......................................................................
vc/amd/fsp/phoenix/platform_descriptors: add PCIe gen 4 link speed
Phoenix supports up to PCIe gen 4 link speeds, so add the missing GEN4
element to the dxio_link_speed_cap enum. The enum value for the PCIe gen
4 link speed was checked against the AGESA reference code.
Bug=b:277815815
TEST=None
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I74f0b79e336206113ade24a87cbd161a12967f56
---
M src/vendorcode/amd/fsp/phoenix/platform_descriptors.h
1 file changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/74378/1
diff --git a/src/vendorcode/amd/fsp/phoenix/platform_descriptors.h b/src/vendorcode/amd/fsp/phoenix/platform_descriptors.h
index a260138..368794a 100644
--- a/src/vendorcode/amd/fsp/phoenix/platform_descriptors.h
+++ b/src/vendorcode/amd/fsp/phoenix/platform_descriptors.h
@@ -32,6 +32,7 @@
GEN1,
GEN2,
GEN3,
+ GEN4,
GEN_INVALID // Max Gen for boundary check
};
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Change subject: soc/intel/cannonlake: Allow SoC to choose CAR mode (eNEM/NEM)
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Is there some document to tell on which platforms this can be done?
typically all client skus like CML and WHL that chromeos team worked has eNEM enabled.
We never worked on any desktop platform like CFL hence, i assume eNEM never tested there.
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Change subject: soc/intel/cannonlake: Allow SoC to choose CAR mode (eNEM/NEM)
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Patch Set 1:
(1 comment)
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PS1:
Is there some document to tell on which platforms this can be done?
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Change subject: soc/intel/cmd/block/cse: Add config option for storing fw version info
......................................................................
Patch Set 11:
(1 comment)
File src/soc/intel/common/block/cse/Kconfig:
https://review.coreboot.org/c/coreboot/+/74255/comment/a21203df_2d15f412
PS9, Line 56:
> … from payload or OS, as that information can only be retrieved in the firmware stage(?) due to security measures(?).
I don't think so, cbmem id can be retrieve from os (in read-only format)
cbmem -r <cbmem_id>
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