coreboot-gerrit April 2023

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[S] Change in coreboot[master]: soc/intel/common: Fix acpigen use for processor Device
by Arthur Heymans (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Patrick Rudolph, Paul Menzel, Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74395 ) Change subject: soc/intel/common: Fix acpigen use for processor Device ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74395 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4e21732ac31076a1a97a774e03c8466d17c5f29 Gerrit-Change-Number: 74395 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 17:53:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: intel/i82371eb,speedstep: Use dev_count_cpu()
by Arthur Heymans (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74397 ) Change subject: intel/i82371eb,speedstep: Use dev_count_cpu() ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8582d401c72ad44137f117315c5c6869654c3e99 Gerrit-Change-Number: 74397 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 17:53:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/cmd/block: Implement an API to get firmware partition details
by Subrata Banik (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Dinesh Gehlot. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74005 ) Change subject: soc/intel/cmd/block: Implement an API to get firmware partition details ...................................................................... Patch Set 31: (1 comment) Patchset: PS31: > I wish to revise this CL as there are some gap in this cl 😞 the entire patch train need some modification. -- To view, visit https://review.coreboot.org/c/coreboot/+/74005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 Gerrit-Change-Number: 74005 Gerrit-PatchSet: 31 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 17:48:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/cmd/block: Implement an API to get firmware partition details
by Subrata Banik (Code Review) 13 Apr '23

13 Apr '23

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74005 ) Change subject: soc/intel/cmd/block: Implement an API to get firmware partition details ...................................................................... Patch Set 31: (1 comment) Patchset: PS31: I wish to revise this CL as there are some gap in this cl 😞 -- To view, visit https://review.coreboot.org/c/coreboot/+/74005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 Gerrit-Change-Number: 74005 Gerrit-PatchSet: 31 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 13 Apr 2023 17:47:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/cmd/block: Implement an API to get firmware partition details
by Subrata Banik (Code Review) 13 Apr '23

13 Apr '23

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74005 ) Change subject: soc/intel/cmd/block: Implement an API to get firmware partition details ...................................................................... Patch Set 31: (1 comment) Patchset: PS31: please don't merge -- To view, visit https://review.coreboot.org/c/coreboot/+/74005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 Gerrit-Change-Number: 74005 Gerrit-PatchSet: 31 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 13 Apr 2023 17:47:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex: add variant gpio tables for variant creation
by Paul Fagerburg (Code Review) 13 Apr '23

13 Apr '23

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74257 ) Change subject: mb/google/rex: add variant gpio tables for variant creation ...................................................................... mb/google/rex: add variant gpio tables for variant creation BUG=b:276818954 TEST=new_variant_fulltest.sh rex0 BRANCH=None Signed-off-by: YH Lin <yueherngl(a)google.com> Change-Id: Iebc098f8d480ac3e1835b00861fd844d97f281a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74257 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- A util/mainboard/google/rex0/template/Makefile.inc A util/mainboard/google/rex0/template/gpio.c 2 files changed, 55 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Fagerburg: Looks good to me, approved Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/util/mainboard/google/rex0/template/Makefile.inc b/util/mainboard/google/rex0/template/Makefile.inc new file mode 100644 index 0000000..6c29346 --- /dev/null +++ b/util/mainboard/google/rex0/template/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c diff --git a/util/mainboard/google/rex0/template/gpio.c b/util/mainboard/google/rex0/template/gpio.c new file mode 100644 index 0000000..b6e346f --- /dev/null +++ b/util/mainboard/google/rex0/template/gpio.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <types.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + +static const struct cros_gpio cros_gpios[] = { +}; + +DECLARE_CROS_GPIOS(cros_gpios); + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/74257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebc098f8d480ac3e1835b00861fd844d97f281a8 Gerrit-Change-Number: 74257 Gerrit-PatchSet: 7 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Rosa Franzini <danielt3(a)usp.br> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/cmd/block: Implement an API to get firmware partition details
by Felix Held (Code Review) 13 Apr '23

13 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74005 ) Change subject: soc/intel/cmd/block: Implement an API to get firmware partition details ...................................................................... soc/intel/cmd/block: Implement an API to get firmware partition details This patch retrieves details of a specified firmware partition table. The information retrieved includes the current firmware version and other information about the firmware partition. The patch communicates with the ME using the HECI command to acquire this information. BUG=b:273661726 Test=Verified the changes for ISH partition on nissa board. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74005 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 110 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sridhar Siricilla: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 1aa3454..9a4cd45 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1213,6 +1213,63 @@ } } +static enum cb_err send_get_fpt_partition_info_cmd(enum fpt_partition_id id, + struct fw_version_resp *resp) +{ + enum cse_tx_rx_status ret; + struct fw_version_msg { + struct mkhi_hdr hdr; + enum fpt_partition_id partition_id; + } __packed msg = { + .hdr = { + .group_id = MKHI_GROUP_ID_GEN, + .command = GEN_GET_IMAGE_FW_VERSION, + }, + .partition_id = id, + }; + + /* + * Prerequisites: + * 1) HFSTS1 CWS is Normal + * 2) HFSTS1 COM is Normal + * 3) Only sent after DID (accomplished by compiling this into ramstage) + */ + + if (cse_is_hfs1_com_soft_temp_disable() || !cse_is_hfs1_cws_normal() || + !cse_is_hfs1_com_normal()) { + printk(BIOS_ERR, + "HECI: Prerequisites not met for Get Image Firmware Version command\n"); + return CB_ERR; + } + + size_t resp_size = sizeof(struct fw_version_resp); + ret = heci_send_receive(&msg, sizeof(msg), resp, &resp_size, HECI_MKHI_ADDR); + + if (ret || resp->hdr.result) { + printk(BIOS_ERR, "CSE: Failed to get partition information for %d: 0x%x\n", + id, resp->hdr.result); + return CB_ERR; + } + + return CB_SUCCESS; +} + +enum cb_err cse_get_fpt_partition_info(enum fpt_partition_id id, struct fw_version_resp *resp) +{ + if (vboot_recovery_mode_enabled()) { + printk(BIOS_WARNING, + "CSE: Skip sending Get Image Info command during recovery mode!\n"); + return CB_ERR; + } + + if (id == FPT_PARTITION_NAME_ISHC && !CONFIG(DRIVERS_INTEL_ISH)) { + printk(BIOS_WARNING, "CSE: Info request denied, no ISH partition\n"); + return CB_ERR; + } + + return send_get_fpt_partition_info_cmd(id, resp); +} + #if ENV_RAMSTAGE /* diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index b39ae7f..6b708ca 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -49,6 +49,7 @@ #define MKHI_BUP_COMMON_GET_BOOT_PARTITION_INFO 0x1c #define MKHI_BUP_COMMON_SET_BOOT_PARTITION_INFO 0x1d #define MKHI_BUP_COMMON_DATA_CLEAR 0x20 +#define GEN_GET_IMAGE_FW_VERSION 0x1c /* Get boot performance command id */ #define MKHI_BUP_COMMON_GET_BOOT_PERF_DATA 0x8 @@ -85,6 +86,12 @@ PCI_ME_HFSTS6 = 0x6C, }; +/* CSE partition list */ +enum fpt_partition_id { + FPT_PARTITION_NAME_UNDEFINED = 0x0, + FPT_PARTITION_NAME_ISHC = 0x43485349, +}; + /* MKHI Message Header */ struct mkhi_hdr { uint8_t group_id; @@ -118,6 +125,25 @@ struct me_version fitc; } __packed; +/* Module data from manifest */ +struct flash_partition_data { + enum fpt_partition_id partition_id; + uint8_t reserved1[8]; + struct fw_version version; + uint32_t vendor_id; + uint32_t tcb_svn; + uint32_t arb_svn; + uint32_t vcn; + uint32_t reserved2[13]; +}; + +/* Response header for partition information request */ +struct fw_version_resp { + struct mkhi_hdr hdr; + uint32_t module_count; + struct flash_partition_data manifest_data; +}; + /* CSE RX and TX error status */ enum cse_tx_rx_status { /* @@ -502,4 +528,10 @@ */ enum cb_err cse_get_fw_feature_state(uint32_t *feature_state); +/* + * The function sends a HECI command to get the partition information of the shared ID. + * The retrieved partition is stored in the memory pointed to by the resp pointer. + * The function returns 0 on success and < 0 on failure. + */ +enum cb_err cse_get_fpt_partition_info(enum fpt_partition_id id, struct fw_version_resp *resp); #endif // SOC_INTEL_COMMON_CSE_H -- To view, visit https://review.coreboot.org/c/coreboot/+/74005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 Gerrit-Change-Number: 74005 Gerrit-PatchSet: 31 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/cannonlake: Allow SoC to choose CAR mode (eNEM/NEM)
by Subrata Banik (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Arthur Heymans. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74377 ) Change subject: soc/intel/cannonlake: Allow SoC to choose CAR mode (eNEM/NEM) ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > > > Is there some document to tell on which platforms this can be done? > > > > typically all client skus like CML and WHL that chromeos team worked has eNEM enabled. > > > > We never worked on any desktop platform like CFL hence, i assume eNEM never tested there. > > Makes sense. It would be good to include the reasoning of https://review.coreboot.org/c/coreboot/+/74376 inside either the commit message or as a comment so that the git history has the reasoning included. make sense -- To view, visit https://review.coreboot.org/c/coreboot/+/74377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibeaa4d53279ff9cbcd0b2ac5f2ad71925872355b Gerrit-Change-Number: 74377 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 13 Apr 2023 17:39:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cannonlake: Allow SoC to choose CAR mode (eNEM/NEM)
by Subrata Banik (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Subrata Banik. Hello build bot (Jenkins), Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74377 to look at the new patch set (#2). Change subject: soc/intel/cannonlake: Allow SoC to choose CAR mode (eNEM/NEM) ...................................................................... soc/intel/cannonlake: Allow SoC to choose CAR mode (eNEM/NEM) This patch avoids cannonlake base config to select eNEM for CAR by default. Rather allow other SoC config to choose the applicable CAR mode between eNEM and NEM. CML and WHL select eNEM whereas CFL decided to use NEM for CAR setup. Here is some background about why CFL SoC platform decided to choose NEM over eNEM: It was found that some coffeelake CPUs like Intel i3 9100E fail to enter CAR mode because some MSR used by NEM enhanced are lacking. According to the Intel SDM CPUID.EAX=07h.ECX=0 reg EBX[12 or 15] should indicate the presence of IA32_PAR_ASSOC and CPUID.EAX=10h.ECX[1 or 2] reg ECX[2] should indicate IA32_L3_QOS_CFG and IA32_L2_QOS_CFG respectively but even on a Intel coffeelake CPU that works with the NEM_ENHANCED these CPUID bits are all 0 so there is no way of knowing whether NEM_ENHANCED will work at runtime. Instead just always use regular NEM. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ibeaa4d53279ff9cbcd0b2ac5f2ad71925872355b --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 31 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/74377/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibeaa4d53279ff9cbcd0b2ac5f2ad71925872355b Gerrit-Change-Number: 74377 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: vc/amd/fsp/phoenix/platform_descriptors: add PCIe gen 4 link speed
by Felix Held (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Jason Glenesk, Tim Van Patten. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74378 ) Change subject: vc/amd/fsp/phoenix/platform_descriptors: add PCIe gen 4 link speed ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Oh, nice. I'm glad it was this easy. […] this at least corresponds to what i saw in the reference code. not sure if any work is needed on the fsp side or if everything is already in place there. the reference code also sets in the pspp related port parameters in the equivalent of the port descriptor struct array, but i'd advise against enabling pspp too early; iirc on cezanne enabling pspp caused a bit of trouble at first, so it's not a too great idea to already enable pspp for bringup -- To view, visit https://review.coreboot.org/c/coreboot/+/74378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74f0b79e336206113ade24a87cbd161a12967f56 Gerrit-Change-Number: 74378 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 17:35:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit April 2023