coreboot-gerrit April 2023

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[S] Change in coreboot[master]: AMD binaryPI: Declare IOAPIC IDs
by Kyösti Mälkki (Code Review) 13 Apr '23

13 Apr '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74315 ) Change subject: AMD binaryPI: Declare IOAPIC IDs ...................................................................... AMD binaryPI: Declare IOAPIC IDs There is no longer a relation between MAX_CPUS and IOAPIC IDs, start the cleanup with new declarations. Change-Id: I65888550e359e55402d99e8816ece2061cfcccbc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74315 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/amd/pi/00730F01/acpi_tables.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/amd/pi/00730F01/state_machine.c A src/southbridge/amd/pi/hudson/ioapic.h M src/southbridge/amd/pi/hudson/sm.c 5 files changed, 38 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/northbridge/amd/pi/00730F01/acpi_tables.c b/src/northbridge/amd/pi/00730F01/acpi_tables.c index 1cf7e74..bb510cd 100644 --- a/src/northbridge/amd/pi/00730F01/acpi_tables.c +++ b/src/northbridge/amd/pi/00730F01/acpi_tables.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <arch/ioapic.h> #include <northbridge/amd/nb_common.h> +#include <southbridge/amd/pi/hudson/ioapic.h> unsigned long acpi_fill_madt(unsigned long current) { @@ -10,11 +11,11 @@ current = acpi_create_madt_lapics_with_nmis(current); /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, CONFIG_MAX_CPUS, + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, FCH_IOAPIC_ID, IO_APIC_ADDR, 0); /* TODO: Remove the hardcode */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, CONFIG_MAX_CPUS + 1, + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, GNB_IOAPIC_ID, IO_APIC2_ADDR, 24); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index dab0e72..644e2d5 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -23,6 +23,7 @@ #include <northbridge/amd/nb_common.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <southbridge/amd/pi/hudson/pci_devs.h> +#include <southbridge/amd/pi/hudson/ioapic.h> #include <amdblocks/cpu.h> #define MAX_NODE_NUMS MAX_NODES @@ -221,7 +222,7 @@ static void northbridge_init(struct device *dev) { - setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS + 1); + setup_ioapic((u8 *)IO_APIC2_ADDR, GNB_IOAPIC_ID); } static unsigned long acpi_fill_hest(acpi_hest_t *hest) @@ -253,7 +254,7 @@ ivhd_ioapic->dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS | IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS; - ivhd_ioapic->handle = CONFIG_MAX_CPUS; /* FCH IOAPIC ID */ + ivhd_ioapic->handle = FCH_IOAPIC_ID; ivhd_ioapic->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; current += sizeof(ivrs_ivhd_special_t); @@ -263,7 +264,7 @@ ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; ivhd_ioapic->reserved = 0x0000; ivhd_ioapic->dte_setting = 0x00; - ivhd_ioapic->handle = CONFIG_MAX_CPUS + 1; /* GNB IOAPIC ID */ + ivhd_ioapic->handle = GNB_IOAPIC_ID; ivhd_ioapic->source_dev_id = PCI_DEVFN(0, 1); ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; current += sizeof(ivrs_ivhd_special_t); diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c index ba34dab..0693a5d 100644 --- a/src/northbridge/amd/pi/00730F01/state_machine.c +++ b/src/northbridge/amd/pi/00730F01/state_machine.c @@ -9,6 +9,7 @@ #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/nb_common.h> +#include <southbridge/amd/pi/hudson/ioapic.h> void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { @@ -64,8 +65,8 @@ * when IOMMU build config is enabled otherwise AGESA will skip * it during IOMMU init and IVRS generation. */ - Late->GnbLateConfiguration.GnbIoapicId = CONFIG_MAX_CPUS + 1; - Late->GnbLateConfiguration.FchIoapicId = CONFIG_MAX_CPUS; + Late->GnbLateConfiguration.GnbIoapicId = GNB_IOAPIC_ID; + Late->GnbLateConfiguration.FchIoapicId = FCH_IOAPIC_ID; } /* Code for creating CDIT requires hop count table. If it is not diff --git a/src/southbridge/amd/pi/hudson/ioapic.h b/src/southbridge/amd/pi/hudson/ioapic.h new file mode 100644 index 0000000..757e5c8 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/ioapic.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_IOAPIC_H +#define AMD_BLOCK_IOAPIC_H + +/* Since the old APIC bus isn't used any more, the IOAPIC IDs could be < CONFIG_MAX_CPUS */ +#define FCH_IOAPIC_ID (CONFIG_MAX_CPUS) +#define GNB_IOAPIC_ID (CONFIG_MAX_CPUS + 1) + +#endif /* AMD_BLOCK_IOAPIC_H */ diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index 79d1005..c40bf5e 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -5,6 +5,7 @@ #include <device/pci_ids.h> #include <device/smbus.h> #include <arch/ioapic.h> +#include <southbridge/amd/pi/hudson/ioapic.h> #include "hudson.h" #include "smbus.c" @@ -21,7 +22,7 @@ static void sm_init(struct device *dev) { - setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); + setup_ioapic(VIO_APIC_VADDR, FCH_IOAPIC_ID); } static int lsmbus_recv_byte(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/74315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65888550e359e55402d99e8816ece2061cfcccbc Gerrit-Change-Number: 74315 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/brya/var/brya: Add new GFX devices with custom _PLD
by Won Chung (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Tarun Tuli. Hello Tarun Tuli, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74407 to look at the new patch set (#2). Change subject: mb/google/brya/var/brya: Add new GFX devices with custom _PLD ...................................................................... mb/google/brya/var/brya: Add new GFX devices with custom _PLD Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung(a)google.com> Change-Id: Ia756f842943b8e1f1877db7433641e6bbd05f45b --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/brya0/overridetree.cb 2 files changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/74407/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia756f842943b8e1f1877db7433641e6bbd05f45b Gerrit-Change-Number: 74407 Gerrit-PatchSet: 2 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: vc/amd/fsp/phoenix/platform_descriptors: add PCIe gen 4 link speed
by Tim Van Patten (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Jason Glenesk, Felix Held. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74378 ) Change subject: vc/amd/fsp/phoenix/platform_descriptors: add PCIe gen 4 link speed ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > this at least corresponds to what i saw in the reference code. […] Is it safe to use this enum once this lands, or do we need to wait for confirmation on whether the FSP needs more work? Can/Will you be following up on the FSP side as part of b/277815815, or do we need another bug for that work? -- To view, visit https://review.coreboot.org/c/coreboot/+/74378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74f0b79e336206113ade24a87cbd161a12967f56 Gerrit-Change-Number: 74378 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 13 Apr 2023 18:17:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/brya: Add new GFX devices with custom _PLD
by Won Chung (Code Review) 13 Apr '23

13 Apr '23

Won Chung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74407 ) Change subject: mb/google/brya/var/brya: Add new GFX devices with custom _PLD ...................................................................... mb/google/brya/var/brya: Add new GFX devices with custom _PLD Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung(a)google.com> Change-Id: Ia756f842943b8e1f1877db7433641e6bbd05f45b --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/brya0/overridetree.cb 2 files changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/74407/1 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index f271ef9..f5eb1eb 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -46,6 +46,7 @@ select DRIVERS_INTEL_MIPI_CAMERA select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_CRASHLOG + select DRIVERS_GFX_GENERIC config BOARD_GOOGLE_FELWINTER bool "-> Felwinter" diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index e07fc72..ca09655 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -116,6 +116,30 @@ }" device domain 0 on + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "6" + # DDIA for eDP + register "device[0].name" = ""LCD"" + # DDIB for HDMI + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_custom_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) for port C1 + register "device[3].name" = ""DD03"" + register "device[3].use_custom_pld" = "true" + register "device[3].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + # TCP2 (DP-3) for port C2 + register "device[4].name" = ""DD04"" + register "device[4].use_custom_pld" = "true" + register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" + # TCP3 (DP-4) unused + register "device[5].name" = ""DD05"" + device generic 0 on end + end + end # Integrated Graphics Device device ref dtt on chip drivers/intel/dptf ## sensor information -- To view, visit https://review.coreboot.org/c/coreboot/+/74407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia756f842943b8e1f1877db7433641e6bbd05f45b Gerrit-Change-Number: 74407 Gerrit-PatchSet: 1 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: ec/acpi/ec: replace misleading "recv_ec_data_timeout" console output
by Fred Reitberger (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74381 ) Change subject: ec/acpi/ec: replace misleading "recv_ec_data_timeout" console output ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I521f67517f64fc64e24853d96730c3f9459f1ccc Gerrit-Change-Number: 74381 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 13 Apr 2023 18:09:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: ec/acpi/ec: replace misleading "recv_ec_data_timeout" console output
by Felix Held (Code Review) 13 Apr '23

13 Apr '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74381 ) Change subject: ec/acpi/ec: replace misleading "recv_ec_data_timeout" console output ...................................................................... ec/acpi/ec: replace misleading "recv_ec_data_timeout" console output In the non-timeout case in recv_ec_data_timeout, a message like this one will get printed at BIOS_SPEW log level: "recv_ec_data_timeout: 0x00". The "timeout" part of the function name corresponds to what the function does, but the message will only be printed when not running into the timeout which is a bit misleading and might suggest a problem when there is none. To avoid this possible confusion, don't use the function name in the printk, but use "Data from EC:" instead. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I521f67517f64fc64e24853d96730c3f9459f1ccc --- M src/ec/acpi/ec.c 1 file changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/74381/1 diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c index fbd9acd..f183801 100644 --- a/src/ec/acpi/ec.c +++ b/src/ec/acpi/ec.c @@ -88,7 +88,7 @@ } data = inb(ec_data_reg); - printk(BIOS_SPEW, "%s: 0x%02x\n", __func__, data); + printk(BIOS_SPEW, "Data from EC: 0x%02x\n", data); return data; } -- To view, visit https://review.coreboot.org/c/coreboot/+/74381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I521f67517f64fc64e24853d96730c3f9459f1ccc Gerrit-Change-Number: 74381 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/common: Fix acpigen use for processor Device
by Kyösti Mälkki (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Patrick Rudolph, Paul Menzel. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74395 ) Change subject: soc/intel/common: Fix acpigen use for processor Device ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74395/comment/a8e127cf_06c939f6 PS1, Line 8: > Both work. Sometimes nested acpigen calls get hard to read, so one may prefer to not use pop_len(). Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74395 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4e21732ac31076a1a97a774e03c8466d17c5f29 Gerrit-Change-Number: 74395 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 13 Apr 2023 17:58:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: AMD binaryPI: Use madt_ioapic_from_hw()
by Arthur Heymans (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Michał Żygowski, Kyösti Mälkki, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55570 ) Change subject: AMD binaryPI: Use madt_ioapic_from_hw() ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8ba395bc220fdb691118719f7b32dd7400931f4 Gerrit-Change-Number: 55570 Gerrit-PatchSet: 13 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 13 Apr 2023 17:57:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: AMD binaryPI: Declare IOAPIC IDs
by Arthur Heymans (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Kyösti Mälkki, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74315 ) Change subject: AMD binaryPI: Declare IOAPIC IDs ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65888550e359e55402d99e8816ece2061cfcccbc Gerrit-Change-Number: 74315 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 13 Apr 2023 17:55:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd: Clarify ACPI _PRT entry generation
by Arthur Heymans (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Kyösti Mälkki, Fred Reitberger, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74314 ) Change subject: soc/amd: Clarify ACPI _PRT entry generation ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d862e37424f9fea7f269cd09e9e90056531b643 Gerrit-Change-Number: 74314 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 13 Apr 2023 17:55:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2023