coreboot-gerrit April 2023

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[M] Change in coreboot[master]: soc/intel/: Store CSE firmware version into CBMEM
by Subrata Banik (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Sridhar Siricilla. Subrata Banik has uploaded a new patch set (#13) to the change originally created by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/74256 ) Change subject: soc/intel/: Store CSE firmware version into CBMEM ...................................................................... soc/intel/: Store CSE firmware version into CBMEM The patch implements an API that stores the CSE firmware version in the CBMEM table. The API will be called from RAMSTAGE based on boot state machine depending upon CSE sync config options (`SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE` or `SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE`). BUG=b:273661726 TEST=Able to build and boot google/marasov. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 87 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/74256/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/74256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 Gerrit-Change-Number: 74256 Gerrit-PatchSet: 13 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/cmd/block/cse: Add config option for storing fw version info
by Subrata Banik (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Paul Menzel, Dinesh Gehlot. Subrata Banik has uploaded a new patch set (#12) to the change originally created by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/74255 ) Change subject: soc/intel/cmd/block/cse: Add config option for storing fw version info ...................................................................... soc/intel/cmd/block/cse: Add config option for storing fw version info This patch adds a configuration option, 'SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION', which enables the storage of firmware version information in CBMEM memory. This information can be used to identify the firmware version that is currently installed on the system. The option depends on the `DRIVERS_INTEL_ISH` config and platform should be flexible enough to opt out from enabling this feature. BUG=b:273661726 TEST=Able to build and boot google/marasov. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I78fef45fd2940536b3e91cfd4d184b7635238499 --- M src/soc/intel/common/block/cse/Kconfig 1 file changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/74255/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/74255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78fef45fd2940536b3e91cfd4d184b7635238499 Gerrit-Change-Number: 74255 Gerrit-PatchSet: 12 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/brya: Enable CSE FPT Info config for Marasov, Nissa, Omnigul
by Subrata Banik (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Tarun Tuli. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74386 ) Change subject: mb/google/brya: Enable CSE FPT Info config for Marasov, Nissa, Omnigul ...................................................................... mb/google/brya: Enable CSE FPT Info config for Marasov, Nissa, Omnigul Google Brya variants like Nissa family and Marasov, Omnigul selects `SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION` to store CSE FPT information. BUG=b:273661726 TEST=Able to build and boot google/marasov. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I234b5d272077de9a6f0a9ba69fa015cda7ebd56c --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/74386/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index e588524..942e8b7 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -84,6 +84,7 @@ select SOC_INTEL_ALDERLAKE_PCH_N select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE + select SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_TI50 select SOC_INTEL_COMMON_MMC_OVERRIDE diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 0cb71d4..1cebd91 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -332,6 +332,7 @@ select BOARD_GOOGLE_BASEBOARD_BRYA select SOC_INTEL_RAPTORLAKE select DRIVERS_INTEL_ISH + select SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS config BOARD_GOOGLE_OMNIGUL @@ -340,6 +341,7 @@ select SOC_INTEL_RAPTORLAKE select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS select DRIVERS_INTEL_ISH + select SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION select CHROMEOS_WIFI_SAR if CHROMEOS config BOARD_GOOGLE_CONSTITUTION -- To view, visit https://review.coreboot.org/c/coreboot/+/74386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I234b5d272077de9a6f0a9ba69fa015cda7ebd56c Gerrit-Change-Number: 74386 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/cmn/cse: Store ISH firmware version into CBMEM
by Subrata Banik (Code Review) 13 Apr '23

13 Apr '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74385 ) Change subject: soc/intel/cmn/cse: Store ISH firmware version into CBMEM ...................................................................... soc/intel/cmn/cse: Store ISH firmware version into CBMEM The patch stores the ISH in the CBMEM table. It verifies CSE has been updated by comparing previous and current CSE versions. If it has, the patch updates the previous CSE version with the current CSE version. It then updates the CBMEM table with the current ISH version. BUG=b:273661726 TEST=The current and old CSE and ISH versions are verified on the google/nissa during cold and warm reboots. Additionally, version updates are verified by a debug patch that purposely updated the stored cse version. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: Ie5c5faf926c75b05d189fb1118020fff024fc3e0 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I1985a156080959b86ed3636b764efa673c3ae018 --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 70 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/74385/1 diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 87a78ca..60126fb 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1244,6 +1244,44 @@ return send_get_fpt_partition_info_cmd(id, resp); } +/* +* This API can only be executed after memory has been initialized. This is because the +* command relies on resources that are not available until DRAM initialization command +* has been sent. +*/ +static void store_ish_version(void) +{ + if (vboot_recovery_mode_enabled()) + return; + + struct cse_fw_partition_info *version; + version = cbmem_find(CBMEM_ID_CSE_PARTITION_VERSION); + + /* + * Compare if stored cse version (from the previous boot) is same as current + * running cse version. + */ + if (memcmp(&version->ish_partition_info.prev_cse_fw_version, + &version->cur_cse_fw_version, sizeof(struct fw_version))) { + /* + * Current running CSE version is different than previous stored CSE version + * which could be due to CSE update or rollback, hence, need to send ISHC + * partition info cmd to know the currently running ISH version. + */ + + struct fw_version_resp resp; + if (cse_get_fpt_partition_info(FPT_PARTITION_NAME_ISHC, &resp) == CB_SUCCESS) { + /* Update stored cse version with current version */ + cse_copy_fw_version(&(version->ish_partition_info.prev_cse_fw_version), + &(version->cur_cse_fw_version)); + + /* Since cse version has been updated, ish version needs to be updated. */ + cse_copy_fw_version(&(version->ish_partition_info.cur_ish_fw_version), + &(resp.manifest_data.version)); + } + } +} + static void ramstage_cse_fw_sync(void *unused) { bool s3wake; @@ -1254,8 +1292,10 @@ cse_fw_sync(); timestamp_add_now(TS_CSE_FW_SYNC_END); - if (CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION)) + if (CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION)) { store_cse_rw_fw_version(); + store_ish_version(); + } } } @@ -1267,10 +1307,12 @@ if (s3wake) return; - /* Store the CSE RW Firmware Version into CBMEM */ + /* Store the CSE/ISH RW Firmware Version into CBMEM */ if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) - && CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION)) + && CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION)) { store_cse_rw_fw_version(); + store_ish_version(); + } } BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, ramstage_store_cse_fpt_info, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/74385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1985a156080959b86ed3636b764efa673c3ae018 Gerrit-Change-Number: 74385 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/: Store CSE firmware version into CBMEM
by Subrata Banik (Code Review) 13 Apr '23

13 Apr '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74384 ) Change subject: soc/intel/: Store CSE firmware version into CBMEM ...................................................................... soc/intel/: Store CSE firmware version into CBMEM The patch implements an API that stores the CSE firmware version in the CBMEM table. The API will be called from RAMSTAGE based on boot state machine depending upon CSE sync config options (`SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE` or `SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE`). BUG=b:273661726 TEST=Able to build and boot google/marasov. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I93e1fc60ae30fb330b48cbaeb6da32d727e7c009 --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 90 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/74384/1 diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h index fa5c8d9..4162d84 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h @@ -85,6 +85,7 @@ #define CBMEM_ID_MEM_CHIP_INFO 0x5048434D #define CBMEM_ID_AMD_STB 0x5f425453 #define CBMEM_ID_AMD_MP2 0x5f32504d +#define CBMEM_ID_CSE_PARTITION_VERSION 0x43535056 #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ @@ -163,5 +164,6 @@ { CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"},\ { CBMEM_ID_MEM_CHIP_INFO, "MEM CHIP INFO"},\ { CBMEM_ID_AMD_STB, "AMD STB"},\ - { CBMEM_ID_AMD_MP2, "AMD MP2 BUFFER"} + { CBMEM_ID_AMD_MP2, "AMD MP2 BUFFER"},\ + { CBMEM_ID_CSE_PARTITION_VERSION, "CSE PARTITION VERSION"} #endif /* _CBMEM_ID_H_ */ diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 4cc9e19..87a78ca 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1152,6 +1152,41 @@ } } +static enum cb_err cse_copy_fw_version(struct fw_version *dst, const struct fw_version *src) +{ + if (src == NULL || dst == NULL) { + printk(BIOS_WARNING, "CSE: NULL value pointer provided for fw version copy.\n"); + return CB_ERR_ARG; + } + + dst->major = src->major; + dst->minor = src->minor; + dst->hotfix = src->hotfix; + dst->build = src->build; + + return CB_SUCCESS; +} + +/* + * Helper function that stores current CSE firmware version to CBMEM memory, + * except during recovery mode. + */ +static void store_cse_rw_fw_version(void) +{ + if (vboot_recovery_mode_enabled()) + return; + + struct get_bp_info_rsp cse_bp_info; + + if (cse_get_bp_info(&cse_bp_info) != CB_SUCCESS) + return; + + const struct cse_bp_entry *cse_bp = cse_get_bp_entry(RW, &cse_bp_info.bp_info); + struct cse_fw_partition_info *version; + version = cbmem_add(CBMEM_ID_CSE_PARTITION_VERSION, sizeof(*version)); + cse_copy_fw_version(&(version->cur_cse_fw_version), &(cse_bp->fw_ver)); +} + static enum cb_err send_get_fpt_partition_info_cmd(enum fpt_partition_id id, struct fw_version_resp *resp) { @@ -1218,7 +1253,25 @@ timestamp_add_now(TS_CSE_FW_SYNC_START); cse_fw_sync(); timestamp_add_now(TS_CSE_FW_SYNC_END); + + if (CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION)) + store_cse_rw_fw_version(); } } +static void ramstage_store_cse_fpt_info(void *unused) +{ + bool s3wake; + s3wake = acpi_get_sleep_type() == ACPI_S3; + + if (s3wake) + return; + + /* Store the CSE RW Firmware Version into CBMEM */ + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) + && CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION)) + store_cse_rw_fw_version(); +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, ramstage_store_cse_fpt_info, NULL); BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, ramstage_cse_fw_sync, NULL); diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 6b708ca..47f86ea 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -144,6 +144,18 @@ struct flash_partition_data manifest_data; }; +/* ISHC version */ +struct cse_fw_ish_version_info { + struct fw_version prev_cse_fw_version; + struct fw_version cur_ish_fw_version; +}; + +/* CSE and ISHC version */ +struct cse_fw_partition_info { + struct fw_version cur_cse_fw_version; + struct cse_fw_ish_version_info ish_partition_info; +}; + /* CSE RX and TX error status */ enum cse_tx_rx_status { /* -- To view, visit https://review.coreboot.org/c/coreboot/+/74384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93e1fc60ae30fb330b48cbaeb6da32d727e7c009 Gerrit-Change-Number: 74384 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/cmd/block/cse: Add config option for storing fw version info
by Subrata Banik (Code Review) 13 Apr '23

13 Apr '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74383 ) Change subject: soc/intel/cmd/block/cse: Add config option for storing fw version info ...................................................................... soc/intel/cmd/block/cse: Add config option for storing fw version info This patch adds a configuration option, 'SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION', which enables the storage of firmware version information in CBMEM memory. This information can be used to identify the firmware version that is currently installed on the system. The option depends on the `DRIVERS_INTEL_ISH` config and platform should be flexible enough to opt out from enabling this feature. BUG=b:273661726 TEST=Able to build and boot google/marasov. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I1678387261050b4b88b43860e1b988b135e47a98 --- M src/soc/intel/common/block/cse/Kconfig 1 file changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/74383/1 diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 33d703f..b84942e 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -45,6 +45,15 @@ Use this config for SoC platform prior to CNL PCH (with postboot_sai implemented) to make `HECI1` device disable using private configuration register (PCR) write. +config SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION + bool + default n + depends on DRIVERS_INTEL_ISH + help + This configuration option stores CSE FPT partitions' version in CBMEM memory. + This information can be used to identify the currently running firmware partition + version. + config SOC_INTEL_CSE_SEND_EOP_EARLY bool "CSE send EOP early" depends on SOC_INTEL_COMMON_BLOCK_CSE -- To view, visit https://review.coreboot.org/c/coreboot/+/74383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1678387261050b4b88b43860e1b988b135e47a98 Gerrit-Change-Number: 74383 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/cmn/cse: Move API to get FW partition info into cse_lite.c
by Subrata Banik (Code Review) 13 Apr '23

13 Apr '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74382 ) Change subject: soc/intel/cmn/cse: Move API to get FW partition info into cse_lite.c ...................................................................... soc/intel/cmn/cse: Move API to get FW partition info into cse_lite.c The patch moves API that gets the CSE FW partition information into CSE Lite specific file aka cse_lite.c because the consumer of this API is the cse_lite specific ChromeOS devices hence, it's meaningful to move the cse lite specific implementation inside cse_lite.c file. TEST=Able to build and boot google/marasov with this code change. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I49ffaec467f6fb24327de3b2882e37bf31eeb7cf --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_lite.c 2 files changed, 74 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/74382/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 9a4cd45..1aa3454 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1213,63 +1213,6 @@ } } -static enum cb_err send_get_fpt_partition_info_cmd(enum fpt_partition_id id, - struct fw_version_resp *resp) -{ - enum cse_tx_rx_status ret; - struct fw_version_msg { - struct mkhi_hdr hdr; - enum fpt_partition_id partition_id; - } __packed msg = { - .hdr = { - .group_id = MKHI_GROUP_ID_GEN, - .command = GEN_GET_IMAGE_FW_VERSION, - }, - .partition_id = id, - }; - - /* - * Prerequisites: - * 1) HFSTS1 CWS is Normal - * 2) HFSTS1 COM is Normal - * 3) Only sent after DID (accomplished by compiling this into ramstage) - */ - - if (cse_is_hfs1_com_soft_temp_disable() || !cse_is_hfs1_cws_normal() || - !cse_is_hfs1_com_normal()) { - printk(BIOS_ERR, - "HECI: Prerequisites not met for Get Image Firmware Version command\n"); - return CB_ERR; - } - - size_t resp_size = sizeof(struct fw_version_resp); - ret = heci_send_receive(&msg, sizeof(msg), resp, &resp_size, HECI_MKHI_ADDR); - - if (ret || resp->hdr.result) { - printk(BIOS_ERR, "CSE: Failed to get partition information for %d: 0x%x\n", - id, resp->hdr.result); - return CB_ERR; - } - - return CB_SUCCESS; -} - -enum cb_err cse_get_fpt_partition_info(enum fpt_partition_id id, struct fw_version_resp *resp) -{ - if (vboot_recovery_mode_enabled()) { - printk(BIOS_WARNING, - "CSE: Skip sending Get Image Info command during recovery mode!\n"); - return CB_ERR; - } - - if (id == FPT_PARTITION_NAME_ISHC && !CONFIG(DRIVERS_INTEL_ISH)) { - printk(BIOS_WARNING, "CSE: Info request denied, no ISH partition\n"); - return CB_ERR; - } - - return send_get_fpt_partition_info_cmd(id, resp); -} - #if ENV_RAMSTAGE /* diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 4a624e6..4cc9e19 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1152,6 +1152,63 @@ } } +static enum cb_err send_get_fpt_partition_info_cmd(enum fpt_partition_id id, + struct fw_version_resp *resp) +{ + enum cse_tx_rx_status ret; + struct fw_version_msg { + struct mkhi_hdr hdr; + enum fpt_partition_id partition_id; + } __packed msg = { + .hdr = { + .group_id = MKHI_GROUP_ID_GEN, + .command = GEN_GET_IMAGE_FW_VERSION, + }, + .partition_id = id, + }; + + /* + * Prerequisites: + * 1) HFSTS1 CWS is Normal + * 2) HFSTS1 COM is Normal + * 3) Only sent after DID (accomplished by compiling this into ramstage) + */ + + if (cse_is_hfs1_com_soft_temp_disable() || !cse_is_hfs1_cws_normal() || + !cse_is_hfs1_com_normal()) { + printk(BIOS_ERR, + "HECI: Prerequisites not met for Get Image Firmware Version command\n"); + return CB_ERR; + } + + size_t resp_size = sizeof(struct fw_version_resp); + ret = heci_send_receive(&msg, sizeof(msg), resp, &resp_size, HECI_MKHI_ADDR); + + if (ret || resp->hdr.result) { + printk(BIOS_ERR, "CSE: Failed to get partition information for %d: 0x%x\n", + id, resp->hdr.result); + return CB_ERR; + } + + return CB_SUCCESS; +} + +enum cb_err cse_get_fpt_partition_info(enum fpt_partition_id id, struct fw_version_resp *resp) +{ + if (vboot_recovery_mode_enabled()) { + printk(BIOS_WARNING, + "CSE: Skip sending Get Image Info command during recovery mode!\n"); + return CB_ERR; + } + + if (id == FPT_PARTITION_NAME_ISHC && !CONFIG(DRIVERS_INTEL_ISH)) { + printk(BIOS_WARNING, "CSE: Info request denied, no ISH partition\n"); + return CB_ERR; + } + + return send_get_fpt_partition_info_cmd(id, resp); +} + static void ramstage_cse_fw_sync(void *unused) { bool s3wake; -- To view, visit https://review.coreboot.org/c/coreboot/+/74382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49ffaec467f6fb24327de3b2882e37bf31eeb7cf Gerrit-Change-Number: 74382 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/cmn/cse: Implement an API to get ISH version
by Subrata Banik (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Tarun Tuli, Paul Menzel, Sridhar Siricilla. Subrata Banik has uploaded a new patch set (#13) to the change originally created by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/74209 ) Change subject: soc/intel/cmn/cse: Implement an API to get ISH version ...................................................................... soc/intel/cmn/cse: Implement an API to get ISH version This patch adds an API that will fetch the current ISH version from CBMEM. BUG=b:273661726 Test=The ISHC version, 5.4.2.7779, was retrieved on the google/nivviks. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: Ib3f983d5de5b169474bcdb1e9e2934174a9dadf8 --- M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/74209/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/74209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3f983d5de5b169474bcdb1e9e2934174a9dadf8 Gerrit-Change-Number: 74209 Gerrit-PatchSet: 13 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd: Clarify ACPI _PRT entry generation
by Kyösti Mälkki (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74314 ) Change subject: soc/amd: Clarify ACPI _PRT entry generation ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/common/block/pci/acpi_prt.c: https://review.coreboot.org/c/coreboot/+/74314/comment/cfe364e5_66640f2b PS2, Line 10: /* GNB IO-APIC is located after the FCH IO-APIC */ > the existing comment works, but i'd reword this a bit; maybe something like: […] In theory, it is the sum of all the previously listed IOAPICs' vector counts from the MADT. Far fetched, but in the specs IOAPICs do not need to be on-board devices, thus I don't want to assume the GNB immediately following the FCH. So there is room for improvement here, GNB_GSI_BASE would become a gsi_base input parameter to this function, making it no longer GNB specific but something that we may be able to move under acpi/. We currently completely lack IOAPIC device nodes, so revisit later? -- To view, visit https://review.coreboot.org/c/coreboot/+/74314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d862e37424f9fea7f269cd09e9e90056531b643 Gerrit-Change-Number: 74314 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 13 Apr 2023 20:39:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/apollolake: Communicate with the PMC over Trusted Sideband
by Sean Rhodes (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Felix Singer, Arthur Heymans. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67076 ) Change subject: soc/intel/apollolake: Communicate with the PMC over Trusted Sideband ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/apollolake/acpi/pmc_ipc.asl: https://review.coreboot.org/c/coreboot/+/67076/comment/b12f2232_a1db898c PS7, Line 44: Or (ShiftLeft (And (Arg0, 0xff), 0), Local0, Local0) /* 7:0 Command ID */ > The shift operation is left, but otherwise it looks good […] Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/67076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide33c2deca4c254a18e4878d22e8f1279b39428e Gerrit-Change-Number: 67076 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 13 Apr 2023 20:11:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: comment

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