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Change subject: security/vboot: Add function to clear recovery request
......................................................................
Patch Set 3:
(2 comments)
File src/security/vboot/bootmode.c:
https://review.coreboot.org/c/coreboot/+/74343/comment/7a5b0265_517afed8
PS3, Line 26: if (!vboot_recovery_mode_enabled())
FWIW in vb2api_kernel_phase2() we call it unconditionally without checking this first (it doesn't hurt in the non-recovery case). Probably best to do the same here for consistency (I think otherwise you can get the subcode stuck for longer than intended in some cases).
https://review.coreboot.org/c/coreboot/+/74343/comment/5c03931a_60ccc3f8
PS3, Line 34: save_vbnv_flash(ctx->nvdata);
It would be good to not have to do this here. Currently this is called from BS_POST_DEVICE/ON_EXIT, so probably best to just make sure this gets called before that (e.g. POST_DEVICE/ON_ENTRY).
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Change subject: mb/msi/ms_7d25: Clear recovery request in mainboard_final
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
It feels a bit wrong to do this from mainboard code. Mainboard code is usually just supposed to be about supporting the hardware, not about boot policy or what payload you want to run or stuff like that. There's no fundamental reason why for your mainboard hardware this should be called here when for others it isn't... it has more to do with what payload you run and how the rest of your firmware stack looks.
I think it would probably be more appropriate to implement this in generic code (vboot/bootmode.c sounds fine), maybe as a late ramstage boot state hook, controlled by a separate menuconfig-visible Kconfig so users can choose what makes sense for their platform. You could make it `default y if !CHROMEOS`, that should do the right thing for most use cases.
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Change subject: soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA
......................................................................
Patch Set 6:
(1 comment)
File src/soc/amd/common/block/lpc/spi_dma.c:
https://review.coreboot.org/c/coreboot/+/74334/comment/1adec209_cc5dce2d
PS4, Line 54: can_use_dma
> Atleast the source and dest are 64 byte aligned and the size is > 64 bytes. […]
Marking this comment as resolved.
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Change subject: soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74334/comment/4524ae34_582a3c62
PS4, Line 13: de-compression
> typo: de-compressed
Done
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Jason Glenesk, Martin Roth, Fred Reitberger, Tim Van Patten, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74334
to look at the new patch set (#6).
Change subject: soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA
......................................................................
soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA
CBFS library performs memory mapped access of the files during loading,
verification and de-compression. Even with MTRRs configured correctly,
first few file access through memory map are taking longer times to
load. Update the SPI DMA driver to load the files into CBFS cache, so
that they can be verified and de-compressed with less overhead. This
saves ~60 ms in boot time.
BUG=None
TEST=Build Skyrim BIOS image and boot to OS. Observe ~60 ms improvement
with the boot time. Performing additional test to confirm there are no
regressions.
Before:
=======
970:loading FSP-M
15:starting LZMA decompress (ignore for x86) 760,906 (60,035)
16:finished LZMA decompress (ignore for x86) 798,787 (37,881)
8:starting to load ramstage
17:starting LZ4 decompress (ignore for x86) 1,050,093 (13,790)
18:finished LZ4 decompress (ignore for x86) 1,054,086 (3,993)
971:loading FSP-S
17:starting LZ4 decompress (ignore for x86) 1,067,778 (3,313)
18:finished LZ4 decompress (ignore for x86) 1,068,022 (244)
90:starting to load payload
17:starting LZ4 decompress (ignore for x86) 1,302,155 (11,285)
18:finished LZ4 decompress (ignore for x86) 1,303,938 (1,783)
After:
======
970:loading FSP-M
15:starting LZMA decompress (ignore for x86) 709,542 (12,178)
16:finished LZMA decompress (ignore for x86) 739,379 (29,837)
8:starting to load ramstage
17:starting LZ4 decompress (ignore for x86) 1,001,316 (12,368)
18:finished LZ4 decompress (ignore for x86) 1,001,971 (655)
971:loading FSP-S
17:starting LZ4 decompress (ignore for x86) 1,016,514 (3,031)
18:finished LZ4 decompress (ignore for x86) 1,016,722 (207)
90:starting to load payload
17:starting LZ4 decompress (ignore for x86) 1,244,602 (10,313)
18:finished LZ4 decompress (ignore for x86) 1,244,831 (228)
Change-Id: Ie30b6324f9977261c60e55ed509e979ef290f1f1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/soc/amd/common/block/lpc/spi_dma.c
M src/soc/amd/mendocino/Kconfig
2 files changed, 88 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/74334/6
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Change subject: Update vboot submodule to upstream main
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA
......................................................................
Patch Set 5:
(3 comments)
File src/soc/amd/common/block/lpc/spi_dma.c:
https://review.coreboot.org/c/coreboot/+/74334/comment/8d2224c1_0a9dd17d
PS4, Line 218: if (!CONFIG_CBFS_CACHE_SIZE)
> Correct. […]
Usage model has been:
1) Map the space (rdev_map_full)
2) Consume from the mapped space
3) Unmap it.
So the cbfs_cache gets released after the use. Also for FSP-M, once it is loaded into cbfs_cache, it is possible to explore other faster decompression options like LZ4. Without that, we will have to live with LZMA.
Your comment about ref1 is fair. I have addressed it.
https://review.coreboot.org/c/coreboot/+/74334/comment/d4bbd8fe_a467867d
PS4, Line 223: printk(BIOS_INFO, "%s: Could not allocate from memory pool\n", __func__);
> Please log `size` here also, so we know how much we're trying to allocate and whether it even has a […]
Done
https://review.coreboot.org/c/coreboot/+/74334/comment/a1eb3547_c2b9d79f
PS4, Line 230: mem_pool_free(&cbfs_cache, mapping);
: /* Fall-back to memory map */
: return &mdev->base[offset];
> ref1
Done
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Jason Glenesk, Martin Roth, Fred Reitberger, Tim Van Patten, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74334
to look at the new patch set (#5).
Change subject: soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA
......................................................................
soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA
CBFS library performs memory mapped access of the files during loading,
verification and de-compression. Even with MTRRs configured correctly,
first few file access through memory map are taking longer times to
load. Update the SPI DMA driver to load the files into CBFS cache, so
that they can be verified and de-compression with less overhead. This
saves ~60 ms in boot time.
BUG=None
TEST=Build Skyrim BIOS image and boot to OS. Observe ~60 ms improvement
with the boot time. Performing additional test to confirm there are no
regressions.
Before:
=======
970:loading FSP-M
15:starting LZMA decompress (ignore for x86) 760,906 (60,035)
16:finished LZMA decompress (ignore for x86) 798,787 (37,881)
8:starting to load ramstage
17:starting LZ4 decompress (ignore for x86) 1,050,093 (13,790)
18:finished LZ4 decompress (ignore for x86) 1,054,086 (3,993)
971:loading FSP-S
17:starting LZ4 decompress (ignore for x86) 1,067,778 (3,313)
18:finished LZ4 decompress (ignore for x86) 1,068,022 (244)
90:starting to load payload
17:starting LZ4 decompress (ignore for x86) 1,302,155 (11,285)
18:finished LZ4 decompress (ignore for x86) 1,303,938 (1,783)
After:
======
970:loading FSP-M
15:starting LZMA decompress (ignore for x86) 709,542 (12,178)
16:finished LZMA decompress (ignore for x86) 739,379 (29,837)
8:starting to load ramstage
17:starting LZ4 decompress (ignore for x86) 1,001,316 (12,368)
18:finished LZ4 decompress (ignore for x86) 1,001,971 (655)
971:loading FSP-S
17:starting LZ4 decompress (ignore for x86) 1,016,514 (3,031)
18:finished LZ4 decompress (ignore for x86) 1,016,722 (207)
90:starting to load payload
17:starting LZ4 decompress (ignore for x86) 1,244,602 (10,313)
18:finished LZ4 decompress (ignore for x86) 1,244,831 (228)
Change-Id: Ie30b6324f9977261c60e55ed509e979ef290f1f1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/soc/amd/common/block/lpc/spi_dma.c
M src/soc/amd/mendocino/Kconfig
2 files changed, 88 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/74334/5
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