coreboot-gerrit April 2023

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[S] Change in coreboot[master]: mb/google/rex: add variant gpio tables for variant creation
by Kapil Porwal (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: YH Lin, Tarun Tuli, Daniel Rosa Franzini. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74257 ) Change subject: mb/google/rex: add variant gpio tables for variant creation ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebc098f8d480ac3e1835b00861fd844d97f281a8 Gerrit-Change-Number: 74257 Gerrit-PatchSet: 6 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Rosa Franzini <danielt3(a)usp.br> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Daniel Rosa Franzini <danielt3(a)usp.br> Gerrit-Comment-Date: Thu, 13 Apr 2023 17:20:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: add variant gpio tables for variant creation
by Paul Fagerburg (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: YH Lin, Tarun Tuli, Daniel Rosa Franzini, Kapil Porwal. Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74257 ) Change subject: mb/google/rex: add variant gpio tables for variant creation ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebc098f8d480ac3e1835b00861fd844d97f281a8 Gerrit-Change-Number: 74257 Gerrit-PatchSet: 6 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Rosa Franzini <danielt3(a)usp.br> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Daniel Rosa Franzini <danielt3(a)usp.br> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 17:13:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cannonlake: Allow SoC to choose CAR mode (eNEM/NEM)
by Arthur Heymans (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Subrata Banik. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74377 ) Change subject: soc/intel/cannonlake: Allow SoC to choose CAR mode (eNEM/NEM) ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: > > Is there some document to tell on which platforms this can be done? > > typically all client skus like CML and WHL that chromeos team worked has eNEM enabled. > > We never worked on any desktop platform like CFL hence, i assume eNEM never tested there. Makes sense. It would be good to include the reasoning of https://review.coreboot.org/c/coreboot/+/74376 inside either the commit message or as a comment so that the git history has the reasoning included. -- To view, visit https://review.coreboot.org/c/coreboot/+/74377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibeaa4d53279ff9cbcd0b2ac5f2ad71925872355b Gerrit-Change-Number: 74377 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 17:10:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vc/amd/fsp/phoenix/platform_descriptors: add PCIe gen 4 link speed
by Jon Murphy (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Jason Glenesk, Felix Held. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74378 ) Change subject: vc/amd/fsp/phoenix/platform_descriptors: add PCIe gen 4 link speed ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74f0b79e336206113ade24a87cbd161a12967f56 Gerrit-Change-Number: 74378 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 13 Apr 2023 16:54:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/myst: Add initial fch irq routing
by Jon Murphy (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Karthik Ramasubramanian, Mark Hasemeyer. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74109 ) Change subject: mb/google/myst: Add initial fch irq routing ...................................................................... Patch Set 29: (1 comment) File src/mainboard/google/myst/mainboard.c: https://review.coreboot.org/c/coreboot/+/74109/comment/b7167985_7a19ac9b PS29, Line 12: accessed via I/O ports 0xc00/0xc01. */ > Can you please cite the source for the routing table? See https://review.coreboot.org/c/coreboot/+/74109/5/src/mainboard/google/myst/… This is a copy/paste from Skyrim and MI. Only deltas are as required for what wasn't supported by Phoenix -- To view, visit https://review.coreboot.org/c/coreboot/+/74109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic81c3cbfbb30a0beb3c4083624cf19abe6d1e694 Gerrit-Change-Number: 74109 Gerrit-PatchSet: 29 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 16:40:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/meteoerlake: set power limits dynamically
by Sumeet R Pawnikar (Code Review) 13 Apr '23

13 Apr '23

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74380 ) Change subject: soc/intel/meteoerlake: set power limits dynamically ...................................................................... soc/intel/meteoerlake: set power limits dynamically Set power limit values dynamically based on Meteor Lake CPU TDP and PCI ID of SKU. BRANCH=None BUG=b:270664854 TEST=Built and verified power limit values on Rex board Change-Id: I20c9bc21dfa79696b07c460dbcedb4fa51838bdb Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/chipset.cb M src/soc/intel/meteorlake/systemagent.c 3 files changed, 63 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/74380/1 diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index d4abed8..5984b27 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -4,6 +4,7 @@ #define _SOC_CHIP_H_ #include <drivers/i2c/designware/dw_i2c.h> +#include <device/pci_ids.h> #include <gpio.h> #include <intelblocks/cfg.h> #include <intelblocks/gspi.h> @@ -19,13 +20,32 @@ /* Types of different SKUs */ enum soc_intel_meteorlake_power_limits { - MTL_P_POWER_LIMITS_1, - MTL_P_POWER_LIMITS_2, - MTL_P_POWER_LIMITS_3, - MTL_P_POWER_LIMITS_4, + MTL_P_682_45W_CORE, + MTL_P_282_CORE, + MTL_P_482_CORE, + MTL_P_682_28W_CORE, MTL_POWER_LIMITS_COUNT }; +/* TDP values for different SKUs */ +enum soc_intel_meteorlake_cpu_tdps { + TDP_15W = 15, + TDP_28W = 28, + TDP_45W = 45 +}; + +/* Mapping of different SKUs based on CPU ID and TDP values */ +static const struct { + unsigned int cpu_id; + enum soc_intel_meteorlake_power_limits limits; + enum soc_intel_meteorlake_cpu_tdps cpu_tdp; +} cpuid_to_mtl[] = { + { PCI_DID_INTEL_MTL_P_ID_1, MTL_P_682_45W_CORE, TDP_45W }, + { PCI_DID_INTEL_MTL_P_ID_2, MTL_P_282_CORE, TDP_15W }, + { PCI_DID_INTEL_MTL_P_ID_3, MTL_P_482_CORE, TDP_28W }, + { PCI_DID_INTEL_MTL_P_ID_4, MTL_P_682_28W_CORE, TDP_28W }, +}; + /* Types of display ports */ enum ddi_ports { DDI_PORT_A, diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb index 0962a7c..5b73898 100644 --- a/src/soc/intel/meteorlake/chipset.cb +++ b/src/soc/intel/meteorlake/chipset.cb @@ -3,14 +3,16 @@ device cpu_cluster 0 on end #FIXME: update values for MTL and enable override in systemagent.c - register "power_limits_config[MTL_P_POWER_LIMITS_2]" = "{ + register "power_limits_config[MTL_P_282_CORE]" = "{ .tdp_pl1_override = 15, - .tdp_pl2_override = 55, + .tdp_pl2_override = 57, + .tdp_pl4 = 101, }" - register "power_limits_config[MTL_P_POWER_LIMITS_1]" = "{ + register "power_limits_config[MTL_P_682_45W_CORE]" = "{ .tdp_pl1_override = 45, .tdp_pl2_override = 115, + .tdp_pl4 = 197, }" # NOTE: if any variant wants to override this value, use the same format diff --git a/src/soc/intel/meteorlake/systemagent.c b/src/soc/intel/meteorlake/systemagent.c index 81e4bed..fc152cf 100644 --- a/src/soc/intel/meteorlake/systemagent.c +++ b/src/soc/intel/meteorlake/systemagent.c @@ -5,7 +5,6 @@ #include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> #include <delay.h> #include <intelblocks/cpulib.h> #include <intelblocks/msr.h> @@ -155,6 +154,8 @@ struct soc_power_limits_config *soc_config; struct device *sa; uint16_t sa_pci_id; + u8 tdp; + size_t i; config_t *config; /* Enable Power Aware Interrupt Routing */ @@ -166,31 +167,24 @@ sa = pcidev_path_on_root(PCI_DEVFN_ROOT); sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF; - /* Choose a power limits configuration based on the SoC SKU type, - * differentiated here based on SA PCI ID. */ - switch (sa_pci_id) { - case PCI_DID_INTEL_MTL_P_ID_1: - soc_config = &config->power_limits_config[MTL_P_POWER_LIMITS_1]; - break; - case PCI_DID_INTEL_MTL_P_ID_2: - soc_config = &config->power_limits_config[MTL_P_POWER_LIMITS_2]; - break; - case PCI_DID_INTEL_MTL_P_ID_3: - soc_config = &config->power_limits_config[MTL_P_POWER_LIMITS_3]; - break; - case PCI_DID_INTEL_MTL_P_ID_4: - soc_config = &config->power_limits_config[MTL_P_POWER_LIMITS_4]; - break; - default: - printk(BIOS_ERR, "unknown SA ID: 0x%4x, skipping power limits configuration\n", + tdp = get_cpu_tdp(); + + /* Choose power limits configuration based on the CPU SA PCI ID and + * CPU TDP value. */ + for (i = 0; i < ARRAY_SIZE(cpuid_to_mtl); i++) { + if (sa_pci_id == cpuid_to_mtl[i].cpu_id && + tdp == cpuid_to_mtl[i].cpu_tdp) { + soc_config = &config->power_limits_config[cpuid_to_mtl[i].limits]; + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); + break; + } + } + + if (i == ARRAY_SIZE(cpuid_to_mtl)) { + printk(BIOS_ERR, "Unknown SA ID: 0x%4x, skipped power limits configuration.\n", sa_pci_id); return; } - - /* Remove once commented line below is enabled */ - (void)soc_config; - /* UPDATEME: Need to enable later */ - //set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); } uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) -- To view, visit https://review.coreboot.org/c/coreboot/+/74380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20c9bc21dfa79696b07c460dbcedb4fa51838bdb Gerrit-Change-Number: 74380 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: vc/amd/fsp/phoenix/platform_descriptors: add PCIe gen 4 link speed
by Tim Van Patten (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Jason Glenesk, Felix Held. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74378 ) Change subject: vc/amd/fsp/phoenix/platform_descriptors: add PCIe gen 4 link speed ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Oh, nice. I'm glad it was this easy. CC'ing Jon in case he wants to update his PCIe config once this has landed. -- To view, visit https://review.coreboot.org/c/coreboot/+/74378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74f0b79e336206113ade24a87cbd161a12967f56 Gerrit-Change-Number: 74378 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 13 Apr 2023 16:26:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA
by Tim Van Patten (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74334 ) Change subject: soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA ...................................................................... Patch Set 4: (2 comments) File src/soc/amd/common/block/lpc/spi_dma.c: https://review.coreboot.org/c/coreboot/+/74334/comment/dbf29f04_156daa30 PS4, Line 218: if (!CONFIG_CBFS_CACHE_SIZE) > By extra copy into the cache, are you referring to cbfs_cache? Correct. `spi_dma_readat_mmap()` will copy into the allocated cache buffer: ``` static ssize_t spi_dma_readat_mmap(const struct region_device *rd, void *b, size_t offset, size_t size) { const struct mem_region_device *mdev; mdev = container_of(rd, __typeof__(*mdev), rdev); memcpy(b, &mdev->base[offset], size); return size; } ``` Do we want this? If so, then we should update the fallback case (see: ref1 below) to perform the same copy, since the data is still available and the cache buffer is still good. https://review.coreboot.org/c/coreboot/+/74334/comment/332fbd2e_2488bf43 PS4, Line 230: mem_pool_free(&cbfs_cache, mapping); : /* Fall-back to memory map */ : return &mdev->base[offset]; ref1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie30b6324f9977261c60e55ed509e979ef290f1f1 Gerrit-Change-Number: 74334 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 13 Apr 2023 16:20:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vc/amd/fsp/phoenix/platform_descriptors: add PCIe gen 4 link speed
by Fred Reitberger (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Jason Glenesk, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74378 ) Change subject: vc/amd/fsp/phoenix/platform_descriptors: add PCIe gen 4 link speed ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74f0b79e336206113ade24a87cbd161a12967f56 Gerrit-Change-Number: 74378 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 13 Apr 2023 16:07:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/apollolake: Communicate with the PMC over Trusted Sideband
by Felix Singer (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Sean Rhodes, Arthur Heymans. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67076 ) Change subject: soc/intel/apollolake: Communicate with the PMC over Trusted Sideband ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/apollolake/acpi/pmc_ipc.asl: https://review.coreboot.org/c/coreboot/+/67076/comment/c2bffe1f_9795235e PS7, Line 44: Or (ShiftLeft (And (Arg0, 0xff), 0), Local0, Local0) /* 7:0 Command ID */ Please use ASL 2.0 syntax -- To view, visit https://review.coreboot.org/c/coreboot/+/67076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide33c2deca4c254a18e4878d22e8f1279b39428e Gerrit-Change-Number: 67076 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 13 Apr 2023 16:00:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2023