coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: vc/google/chromeec/acpi: write OIPG in DECLARE_NO_CROS_GPIOS case
by Felix Held (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Felix Held. Hello build bot (Jenkins), Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74375 to look at the new patch set (#2). Change subject: vc/google/chromeec/acpi: write OIPG in DECLARE_NO_CROS_GPIOS case ...................................................................... vc/google/chromeec/acpi: write OIPG in DECLARE_NO_CROS_GPIOS case When a mainboard selects ACPI_SOC_NVS and CHROMEOS, CHROMEOS_NVS will be selected. This causes vc/google/chromeec/acpi/chromeos.asl to be included in the DSDT and chromeos_acpi_gpio_generate to be called when generating the coreboot SSDT. When a mainboard also uses DECLARE_NO_CROS_GPIOS(), this will cause variant_cros_gpio.count to be 0 and variant_cros_gpio.gpios to be NULL. chromeos_acpi_gpio_generate only checked if the GPIO table was non-NULL, which caused the function to exit early and not generate the OIPG package which causes the kernel to complain about referencing the non-existing OIPG package. To avoid this, only exit in the GPIO table pointer being NULL case if the number of GPIOs is non-0. TEST=Error about missing OIPG ACPI object in dmesg disappears on birman. Before: [ 0.241339] chromeos_acpi: registering CHSW 0 [ 0.241468] ACPI BIOS Error (bug): Could not resolve symbol [\CRHW.GPIO.OIPG], AE_NOT_FOUND (20220331/psargs-330) [ 0.241703] ACPI Error: Aborting method \CRHW.GPIO due to previous error (AE_NOT_FOUND) (20220331/psparse-531) [ 0.241933] chromeos_acpi: failed to retrieve GPIO (5) [ 0.242011] chromeos_acpi: registering VBNV 0 [ 0.242113] chromeos_acpi: registering VBNV 1 [ 0.242284] chromeos_acpi: truncating buffer from 3072 to 1336 [ 0.242462] chromeos_acpi: installed With the patch applied: [ 0.242580] chromeos_acpi: registering CHSW 0 [ 0.242714] chromeos_acpi: registering VBNV 0 [ 0.242817] chromeos_acpi: registering VBNV 1 [ 0.242990] chromeos_acpi: truncating buffer from 3072 to 1336 [ 0.243249] chromeos_acpi: installed Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: Ie340003afb718b1454c2da4a479882b71714c3c7 --- M src/vendorcode/google/chromeos/acpi.c 1 file changed, 45 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/74375/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie340003afb718b1454c2da4a479882b71714c3c7 Gerrit-Change-Number: 74375 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: [UNTESTED] vc/google/chromeec/acpi: write OIPG in DECLARE_NO_CROS_GPI...
by Fred Reitberger (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74375 ) Change subject: [UNTESTED] vc/google/chromeec/acpi: write OIPG in DECLARE_NO_CROS_GPIOS case ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: Tested on amd/birman Kernel dmesg before patch: ``` [ 0.241339] chromeos_acpi: registering CHSW 0 [ 0.241468] ACPI BIOS Error (bug): Could not resolve symbol [\CRHW.GPIO.OIPG], AE_NOT_FOUND (20220331/psargs-330) [ 0.241703] ACPI Error: Aborting method \CRHW.GPIO due to previous error (AE_NOT_FOUND) (20220331/psparse-531) [ 0.241933] chromeos_acpi: failed to retrieve GPIO (5) [ 0.242011] chromeos_acpi: registering VBNV 0 [ 0.242113] chromeos_acpi: registering VBNV 1 [ 0.242284] chromeos_acpi: truncating buffer from 3072 to 1336 [ 0.242462] chromeos_acpi: installed ``` Kernel dmesg after patch: ``` [ 0.242580] chromeos_acpi: registering CHSW 0 [ 0.242714] chromeos_acpi: registering VBNV 0 [ 0.242817] chromeos_acpi: registering VBNV 1 [ 0.242990] chromeos_acpi: truncating buffer from 3072 to 1336 [ 0.243249] chromeos_acpi: installed ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/74375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie340003afb718b1454c2da4a479882b71714c3c7 Gerrit-Change-Number: 74375 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 13 Apr 2023 13:54:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/cbfstool: Correct the definition of struct e820entry
by Paul Menzel (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Bill XIE. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74270 ) Change subject: util/cbfstool: Correct the definition of struct e820entry ...................................................................... Patch Set 5: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74270/comment/81d8fa68_408aac0d PS5, Line 7: Correct the definition of struct e820entry Maybe more specific – no idea if correct: Qualify struct e820entry as packed -- To view, visit https://review.coreboot.org/c/coreboot/+/74270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09955c90e4eec337adca383e628a8821075381d6 Gerrit-Change-Number: 74270 Gerrit-PatchSet: 5 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Comment-Date: Thu, 13 Apr 2023 13:51:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Disable keyboard reset pin
by Felix Held (Code Review) 13 Apr '23

13 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74285 ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/myst: Disable keyboard reset pin ...................................................................... mb/google/myst: Disable keyboard reset pin The keyboard reset is not being used on this board, so disable the functionality. BUG=b:277294460 TEST=None Change-Id: If7fb9ab0c9b1260d342313badb65c55bb9f788c0 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74285 Reviewed-by: Tim Van Patten <timvp(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/myst/Kconfig 1 file changed, 20 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Van Patten: Looks good to me, approved diff --git a/src/mainboard/google/myst/Kconfig b/src/mainboard/google/myst/Kconfig index 956267f..24caa52 100644 --- a/src/mainboard/google/myst/Kconfig +++ b/src/mainboard/google/myst/Kconfig @@ -9,6 +9,7 @@ def_bool y select AMD_SOC_CONSOLE_UART select BOARD_ROMSIZE_KB_16384 + select DISABLE_KEYBOARD_RESET_PIN select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select EC_GOOGLE_CHROMEEC -- To view, visit https://review.coreboot.org/c/coreboot/+/74285 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7fb9ab0c9b1260d342313badb65c55bb9f788c0 Gerrit-Change-Number: 74285 Gerrit-PatchSet: 12 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/skyrim: Hide unused GPP port
by Felix Held (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Martin L Roth, Jason Nien, Eric Lai, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73862 ) Change subject: mb/google/skyrim: Hide unused GPP port ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/skyrim/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/73862/comment/d1439e35_680eebf6 PS1, Line 110: device ref gpp_bridge_3 hidden end > For the case maybe set all gpp hidden in chipset. […] that's probably a good idea, since it makes the mainboard's devicetree file a little more tidy. Martin, since you introduced this, i wonder if you have any strong opinion on this? -- To view, visit https://review.coreboot.org/c/coreboot/+/73862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c1e4c21649610b856469b164ce5b0221f01b7f9 Gerrit-Change-Number: 73862 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 13:45:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: payloads/edk2: Remove ABOVE_4G_MEMORY option
by Sean Rhodes (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Sean Rhodes, Martin L Roth, Benjamin Doron, Stefan Reinauer, Paul Menzel. Hello build bot (Jenkins), Martin L Roth, Benjamin Doron, Stefan Reinauer, Paul Menzel, Lean Sheng Tan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74336 to look at the new patch set (#3). Change subject: payloads/edk2: Remove ABOVE_4G_MEMORY option ...................................................................... payloads/edk2: Remove ABOVE_4G_MEMORY option Remove the ABOVE_4G_MEMORY option as the option was removed in edk2 in commit dc5f2905ebfdf68ae28ce1081d435af0f8641dd9 (UefiPayloadPkg: Always build MemoryTypeInformation HOB for DXE GCD - https://github.com/tianocore/edk2/pull/4231). Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I8d5ee79ef3f7ecfcd1463c612aad2e3d629df22a --- M payloads/external/Makefile.inc M payloads/external/edk2/Kconfig M payloads/external/edk2/Makefile 3 files changed, 15 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/74336/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d5ee79ef3f7ecfcd1463c612aad2e3d629df22a Gerrit-Change-Number: 74336 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: payloads/edk2: Remove ABOVE_4G_MEMORY option
by Lean Sheng Tan (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Sean Rhodes, Martin L Roth, Benjamin Doron, Stefan Reinauer, Paul Menzel. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74336 ) Change subject: payloads/edk2: Remove ABOVE_4G_MEMORY option ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74336/comment/43745afb_2d2fd22f PS2, Line 10: dc5f2905ebfdf68ae28ce1081d435af0f8641dd9 > this is not showing. […] Wait thinking of it, this should be fine. -- To view, visit https://review.coreboot.org/c/coreboot/+/74336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d5ee79ef3f7ecfcd1463c612aad2e3d629df22a Gerrit-Change-Number: 74336 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 13 Apr 2023 13:43:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: payloads/edk2: Remove ABOVE_4G_MEMORY option
by Lean Sheng Tan (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Sean Rhodes, Martin L Roth, Benjamin Doron, Stefan Reinauer, Paul Menzel. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74336 ) Change subject: payloads/edk2: Remove ABOVE_4G_MEMORY option ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74336/comment/b298fb03_f669d569 PS2, Line 10: dc5f2905ebfdf68ae28ce1081d435af0f8641dd9 this is not showing. Maybe could add the edk2 github pull request link? -- To view, visit https://review.coreboot.org/c/coreboot/+/74336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d5ee79ef3f7ecfcd1463c612aad2e3d629df22a Gerrit-Change-Number: 74336 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 13 Apr 2023 13:43:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/myst: Add eSPI configuration
by Felix Held (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Mark Hasemeyer. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74110 ) Change subject: mb/google/myst: Add eSPI configuration ...................................................................... Patch Set 30: (1 comment) File src/mainboard/google/myst/bootblock.c: https://review.coreboot.org/c/coreboot/+/74110/comment/a73bbc63_0dcf9f11 PS30, Line 14: } looking at the espi_gpio_table, you're using spi1 for espi, so you're missing the espi_switch_to_spi1_pads call at the end of this function. see skyrim's mb_set_up_early_espi implementation -- To view, visit https://review.coreboot.org/c/coreboot/+/74110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b40adec78d4e0b596596fa6e2951c79bd3bd8c7 Gerrit-Change-Number: 74110 Gerrit-PatchSet: 30 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 13:42:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [RFC]soc/intel/cannonlake: Use regular NEM for CAR
by Subrata Banik (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Nico Huber, Tarun Tuli, Rizwan Qureshi, Arthur Heymans, Lean Sheng Tan. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74376 ) Change subject: [RFC]soc/intel/cannonlake: Use regular NEM for CAR ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > > > seems like MSR IA32_PQR_ASSOC still exists? or could be wrong? > > > > So not sure which MSR used in NEM_ENHANCED is actually resulting in a hang, but the bits in cpuid are clearly not working as indicator for their presence as they do work on some models where the cpuid bits are 0. > > let me ask Intel is there is any CPUID or other MSR to know if eNEM is supported . can u please try this https://review.coreboot.org/c/coreboot/+/74377 -- To view, visit https://review.coreboot.org/c/coreboot/+/74376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I141cf1543eb59bce86528012a6549101d5911865 Gerrit-Change-Number: 74376 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 13:40:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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coreboot-gerrit April 2023