coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/brya/acpi: Correct _DSM GPS function for revision check
by Felix Held (Code Review) 13 Apr '23

13 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73897 ) Change subject: mb/google/brya/acpi: Correct _DSM GPS function for revision check ...................................................................... mb/google/brya/acpi: Correct _DSM GPS function for revision check The logic was not equals, rather than the intended greater than or equal to for checking the minimum GPS revision. TEST=version check passes as expected now BUG=b:271938907 Signed-off-by: Tarun Tuli <taruntuli(a)google.com> Change-Id: I66bf1fc32295e1b9e9c41c661ea8e395a1592a86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73897 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/acpi/gpu_top.asl 1 file changed, 19 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/acpi/gpu_top.asl b/src/mainboard/google/brya/acpi/gpu_top.asl index c98358f..e23e3cf 100644 --- a/src/mainboard/google/brya/acpi/gpu_top.asl +++ b/src/mainboard/google/brya/acpi/gpu_top.asl @@ -85,7 +85,7 @@ } ElseIf (Arg0 == ToUUID (UUID_GPS)) { - If (ToInteger (Arg1) != REVISION_MIN_GPS) + If (ToInteger (Arg1) >= REVISION_MIN_GPS) { Return (GPS (Arg2, Arg3)) } -- To view, visit https://review.coreboot.org/c/coreboot/+/73897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66bf1fc32295e1b9e9c41c661ea8e395a1592a86 Gerrit-Change-Number: 73897 Gerrit-PatchSet: 6 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/meteorlake: Hook up UPD CnviWifiCore
by Felix Held (Code Review) 13 Apr '23

13 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74306 ) Change subject: soc/intel/meteorlake: Hook up UPD CnviWifiCore ...................................................................... soc/intel/meteorlake: Hook up UPD CnviWifiCore Hook the newly created/exposed CnviWifiCore UPD up as a chip driver. Enable this option by default to maintain the existing behavior. BUG=b:270985197 TEST=Verified by enabling/disabling the UPD on google/rex Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I5b4662c2a064f7c9074797c8a2541dcf1dd686fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/74306 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/chipset.cb M src/soc/intel/meteorlake/fsp_params.c 3 files changed, 29 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index d4abed8..dbe5eb1 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -242,6 +242,9 @@ */ uint8_t serial_io_gspi_cs_state[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + /* CNVi WiFi Core Enable/Disable */ + bool cnvi_wifi_core; + /* CNVi BT Core Enable/Disable */ bool cnvi_bt_core; diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb index 0962a7c..3af284c 100644 --- a/src/soc/intel/meteorlake/chipset.cb +++ b/src/soc/intel/meteorlake/chipset.cb @@ -18,6 +18,9 @@ # putting it under register "common_soc_config" in overridetree.cb file. register "common_soc_config.pch_thermal_trip" = "130" + # Enable CNVi WiFi + register "cnvi_wifi_core" = "true" + device domain 0 on device pci 00.0 alias system_agent on end device pci 01.0 alias pcie_rp12 off end diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index d345f1b..4127ff7 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -562,8 +562,11 @@ { /* CNVi */ s_cfg->CnviMode = is_devfn_enabled(PCI_DEVFN_CNVI_WIFI); + s_cfg->CnviWifiCore = config->cnvi_wifi_core; s_cfg->CnviBtCore = config->cnvi_bt_core; s_cfg->CnviBtAudioOffload = config->cnvi_bt_audio_offload; + /* Assert if CNVi WiFi is enabled without CNVi being enabled. */ + assert(s_cfg->CnviMode || !s_cfg->CnviWifiCore); /* Assert if CNVi BT is enabled without CNVi being enabled. */ assert(s_cfg->CnviMode || !s_cfg->CnviBtCore); /* Assert if CNVi BT offload is enabled without CNVi BT being enabled. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b4662c2a064f7c9074797c8a2541dcf1dd686fe Gerrit-Change-Number: 74306 Gerrit-PatchSet: 5 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/common: Update cpu_apic_info_type struct
by Felix Held (Code Review) 13 Apr '23

13 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74305 ) Change subject: soc/intel/common: Update cpu_apic_info_type struct ...................................................................... soc/intel/common: Update cpu_apic_info_type struct The patch updates total cpu count variable and total P-core count in cpu_apic_info_type structure to `unsigned short int` to address more cores. TEST=Verify the build on Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I46239cc7ad9870e7134955af56b9f6625be2b002 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74305 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/acpi/cpu_hybrid.c 1 file changed, 22 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/cpu_hybrid.c b/src/soc/intel/common/block/acpi/cpu_hybrid.c index e18c288..6e8b641 100644 --- a/src/soc/intel/common/block/acpi/cpu_hybrid.c +++ b/src/soc/intel/common/block/acpi/cpu_hybrid.c @@ -28,14 +28,14 @@ int32_t apic_ids[CONFIG_MAX_CPUS]; /* Total CPU count */ - uint8_t total_cpu_cnt; + uint16_t total_cpu_cnt; /* * Total Performance core count. This will be used * to identify the start of Efficient Cores's * APIC ID list */ - uint8_t perf_cpu_cnt; + uint16_t perf_cpu_cnt; }; static struct cpu_apic_info_type cpu_apic_info; -- To view, visit https://review.coreboot.org/c/coreboot/+/74305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46239cc7ad9870e7134955af56b9f6625be2b002 Gerrit-Change-Number: 74305 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/dedede: Create taranza variant
by Felix Held (Code Review) 13 Apr '23

13 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74295 ) Change subject: mb/google/dedede: Create taranza variant ...................................................................... mb/google/dedede: Create taranza variant Create the taranza variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:277664211 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_TARANZA Change-Id: Id64e48ff2acd6e827fe586a00376183930ddc7e1 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74295 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/taranza/include/variant/ec.h A src/mainboard/google/dedede/variants/taranza/include/variant/gpio.h A src/mainboard/google/dedede/variants/taranza/memory/Makefile.inc A src/mainboard/google/dedede/variants/taranza/memory/dram_id.generated.txt A src/mainboard/google/dedede/variants/taranza/memory/mem_parts_used.txt A src/mainboard/google/dedede/variants/taranza/overridetree.cb 8 files changed, 104 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index ca72da1..e8b3e34 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -114,6 +114,7 @@ default "Gooey" if BOARD_GOOGLE_GOOEY default "Beadrix" if BOARD_GOOGLE_BEADRIX default "Shotzo" if BOARD_GOOGLE_SHOTZO + default "Taranza" if BOARD_GOOGLE_TARANZA config MAX_CPUS int @@ -154,6 +155,7 @@ default "gooey" if BOARD_GOOGLE_GOOEY default "beadrix" if BOARD_GOOGLE_BEADRIX default "shotzo" if BOARD_GOOGLE_SHOTZO + default "taranza" if BOARD_GOOGLE_TARANZA endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index eb69198..8ccd0c7 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -201,3 +201,7 @@ config BOARD_GOOGLE_SHOTZO bool "-> Shotzo" select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 + +config BOARD_GOOGLE_TARANZA + bool "-> Taranza" + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 diff --git a/src/mainboard/google/dedede/variants/taranza/include/variant/ec.h b/src/mainboard/google/dedede/variants/taranza/include/variant/ec.h new file mode 100644 index 0000000..08870e0 --- /dev/null +++ b/src/mainboard/google/dedede/variants/taranza/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/dedede/variants/taranza/include/variant/gpio.h b/src/mainboard/google/dedede/variants/taranza/include/variant/gpio.h new file mode 100644 index 0000000..9078664 --- /dev/null +++ b/src/mainboard/google/dedede/variants/taranza/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/taranza/memory/Makefile.inc b/src/mainboard/google/dedede/variants/taranza/memory/Makefile.inc new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/dedede/variants/taranza/memory/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/dedede/variants/taranza/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/taranza/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/dedede/variants/taranza/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/dedede/variants/taranza/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/taranza/memory/mem_parts_used.txt new file mode 100644 index 0000000..9621137 --- /dev/null +++ b/src/mainboard/google/dedede/variants/taranza/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/dedede/variants/taranza/overridetree.cb b/src/mainboard/google/dedede/variants/taranza/overridetree.cb new file mode 100644 index 0000000..404024b --- /dev/null +++ b/src/mainboard/google/dedede/variants/taranza/overridetree.cb @@ -0,0 +1,42 @@ +chip soc/intel/jasperlake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 15.0 on end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/74295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id64e48ff2acd6e827fe586a00376183930ddc7e1 Gerrit-Change-Number: 74295 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/myst: Enable S0ix
by Felix Held (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Karthik Ramasubramanian, Mark Hasemeyer. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74279 ) Change subject: mb/google/myst: Enable S0ix ...................................................................... Patch Set 12: (1 comment) File src/mainboard/google/myst/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/74279/comment/25dd3d41_9b5060f2 PS12, Line 98: device ref gpp_bridge_2_4 on end # NVMe only semi-related to this patch, but to be done in a follow-up-up patch: you'll need to add the rtd3 chip driver for the nvme ssd for things to work properly around s0i3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cabc2c3ba75f4490da18b861ef2b82ce240860d Gerrit-Change-Number: 74279 Gerrit-PatchSet: 12 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 13:29:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/starlabs/lite/glkr: Disable DPST
by Sean Rhodes (Code Review) 13 Apr '23

13 Apr '23

Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74340 ) Change subject: mb/starlabs/lite/glkr: Disable DPST ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/74340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0e471a1aacd124692bce84ff8b513502c4fa87f Gerrit-Change-Number: 74340 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 13 Apr 2023 13:27:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/starlabs/lite/glk: Disable DPST
by Sean Rhodes (Code Review) 13 Apr '23

13 Apr '23

Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74338 ) Change subject: mb/starlabs/lite/glk: Disable DPST ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/74338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icce4511f5c312619456c16a1a15bc18dd8c6056d Gerrit-Change-Number: 74338 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 13 Apr 2023 13:27:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Enable mp2 device
by Felix Held (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Raul Rangel, Jason Nien, Jon Murphy, Martin Roth, Mark Hasemeyer. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74277 ) Change subject: mb/google/myst: Enable mp2 device ...................................................................... Patch Set 10: (1 comment) File src/mainboard/google/myst/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/74277/comment/64ab871b_8089427c PS10, Line 96: device ref mp2 on end # Sensor Fusion Hub (MP2) would be good to add the devices in the order they are in the chipset devicetree which corresponds to the order of the device functions on the bus and not alphabetically -- To view, visit https://review.coreboot.org/c/coreboot/+/74277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21885c51ff08846b456675090946f381843ef5e6 Gerrit-Change-Number: 74277 Gerrit-PatchSet: 10 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 13:25:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Enable crypto in devicetree
by Felix Held (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Karthik Ramasubramanian, Mark Hasemeyer. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74275 ) Change subject: mb/google/myst: Enable crypto in devicetree ...................................................................... Patch Set 10: (1 comment) File src/mainboard/google/myst/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/74275/comment/cfbd87b1_5ced09ba PS10, Line 93: device ref crypto on end # Crypto Coprocessor would be good to add the devices in the order they are in the chipset devicetree which corresponds to the order of the device functions on the bus and not alphabetically -- To view, visit https://review.coreboot.org/c/coreboot/+/74275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5394c5f9df64642d8633af84cf662652bd1a5cb2 Gerrit-Change-Number: 74275 Gerrit-PatchSet: 10 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 13:25:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Enable audo co-processor in devicetree
by Felix Held (Code Review) 13 Apr '23

13 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Mark Hasemeyer. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74276 ) Change subject: mb/google/myst: Enable audo co-processor in devicetree ...................................................................... Patch Set 9: (1 comment) File src/mainboard/google/myst/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/74276/comment/a96ea306_faf434f6 PS9, Line 93: device ref acp on end # Audio Processor (ACP) would be good to add the devices in the order they are in the chipset devicetree which corresponds to the order of the device functions on the bus and not alphabetically -- To view, visit https://review.coreboot.org/c/coreboot/+/74276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e1749359804960bbd75d869385b9071e7f33be7 Gerrit-Change-Number: 74276 Gerrit-PatchSet: 9 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Thu, 13 Apr 2023 13:24:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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