coreboot-gerrit April 2023

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[S] Change in coreboot[master]: arch/riscv: Fix compiler argument for clang
by Arthur Heymans (Code Review) 19 Apr '23

19 Apr '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74568 ) Change subject: arch/riscv: Fix compiler argument for clang ...................................................................... arch/riscv: Fix compiler argument for clang The suffixes zicsr and zifencei are assumed by default for clang. Change-Id: I75947f614c3600d5d9d461970159f0787fd6c3de Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/riscv/Makefile.inc 1 file changed, 20 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/74568/1 diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index bbbdeb0..cc553c9 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -25,15 +25,21 @@ # suffixes in ARCH_SUFFIX_riscv. simple_riscv_flags = $(riscv_flags) +ifeq ($(CONFIG_COMPILER_GCC),y) +MARCH_SUFFIX=$(ARCH_SUFFIX_riscv) +else +MARCH_SUFFIX= +endif + ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) -riscv_flags += -march=$(CONFIG_RISCV_ARCH)$(ARCH_SUFFIX_riscv) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL) +riscv_flags += -march=$(CONFIG_RISCV_ARCH)$(MARCH_SUFFIX) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL) simple_riscv_flags += -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL) else riscv_flags += $(_rv_flags) simple_riscv_flags += $(_rv_flags) endif -riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH)$(ARCH_SUFFIX_riscv) -mabi=$(CONFIG_RISCV_ABI) +riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH)$(MARCH_SUFFIX) -mabi=$(CONFIG_RISCV_ABI) COMPILER_RT_bootblock = $(shell $(GCC_bootblock) $(simple_riscv_flags) -print-libgcc-file-name) -- To view, visit https://review.coreboot.org/c/coreboot/+/74568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75947f614c3600d5d9d461970159f0787fd6c3de Gerrit-Change-Number: 74568 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/phoenix: Mark PCIe GPP bridges as hidden instead of off
by Matt DeVillier (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Jason Glenesk, Martin L Roth, Fred Reitberger, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74527 ) Change subject: soc/amd/phoenix: Mark PCIe GPP bridges as hidden instead of off ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b7577baa2dbb0ea7ebbcdb1a8ae81770e61d76f Gerrit-Change-Number: 74527 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 19 Apr 2023 19:48:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/mendocino: Mark PCIe GPP bridges as hidden instead of off
by Matt DeVillier (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Fred Reitberger, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74526 ) Change subject: soc/amd/mendocino: Mark PCIe GPP bridges as hidden instead of off ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I517776e4dedc70e957a0c836ab3c2e5d49e156d2 Gerrit-Change-Number: 74526 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 19 Apr 2023 19:48:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/stoneyridge/northbridge: fix indentation in set_mmio_addr_reg
by Felix Held (Code Review) 19 Apr '23

19 Apr '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74567 ) Change subject: soc/amd/stoneyridge/northbridge: fix indentation in set_mmio_addr_reg ...................................................................... soc/amd/stoneyridge/northbridge: fix indentation in set_mmio_addr_reg Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5e067f6fb2bab66d9b2f6965636845dfd8b7cacd --- M src/soc/amd/stoneyridge/northbridge.c 1 file changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/74567/1 diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index b1d2bdd..068ba56 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -50,9 +50,9 @@ /* io range allocation. Limit */ tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00); - pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg); + pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00); - pci_write_config32(SOC_ADDR_DEV, reg, tempreg); + pci_write_config32(SOC_ADDR_DEV, reg, tempreg); } static void read_resources(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/74567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e067f6fb2bab66d9b2f6965636845dfd8b7cacd Gerrit-Change-Number: 74567 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/phoenix: Mark PCIe GPP bridges as hidden instead of off
by Martin L Roth (Code Review) 19 Apr '23

19 Apr '23

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74527 ) Change subject: soc/amd/phoenix: Mark PCIe GPP bridges as hidden instead of off ...................................................................... soc/amd/phoenix: Mark PCIe GPP bridges as hidden instead of off When one of the General-Purpose PCIe bridges is not used, it doesn't show up on the PCI bus at all, so coreboot notes it as an issue in the devicetree. This happens even if the device is marked as off. To solve this, we're marking the GPP bridge devices in devicetree as hidden, so they'll only show up in devicetree if they're actually used on a mainboard. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I7b7577baa2dbb0ea7ebbcdb1a8ae81770e61d76f --- M src/soc/amd/phoenix/chipset.cb 1 file changed, 27 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/74527/1 diff --git a/src/soc/amd/phoenix/chipset.cb b/src/soc/amd/phoenix/chipset.cb index 2d92f14..1e1ad14 100644 --- a/src/soc/amd/phoenix/chipset.cb +++ b/src/soc/amd/phoenix/chipset.cb @@ -11,19 +11,19 @@ device pci 01.0 on end # Dummy Host Bridge, do not disable # The PCIe GPP aliases in this SoC match the device and function numbers - device pci 01.1 alias gpp_bridge_1_1 off ops amd_external_pcie_gpp_ops end - device pci 01.2 alias gpp_bridge_1_2 off ops amd_external_pcie_gpp_ops end - device pci 01.3 alias gpp_bridge_1_3 off ops amd_external_pcie_gpp_ops end - device pci 01.4 alias gpp_bridge_1_4 off ops amd_external_pcie_gpp_ops end + device pci 01.1 alias gpp_bridge_1_1 hidden ops amd_external_pcie_gpp_ops end + device pci 01.2 alias gpp_bridge_1_2 hidden ops amd_external_pcie_gpp_ops end + device pci 01.3 alias gpp_bridge_1_3 hidden ops amd_external_pcie_gpp_ops end + device pci 01.4 alias gpp_bridge_1_4 hidden ops amd_external_pcie_gpp_ops end device pci 02.0 on end # Dummy Host Bridge, do not disable # The PCIe GPP aliases in this SoC match the device and function numbers - device pci 02.1 alias gpp_bridge_2_1 off ops amd_external_pcie_gpp_ops end - device pci 02.2 alias gpp_bridge_2_2 off ops amd_external_pcie_gpp_ops end - device pci 02.3 alias gpp_bridge_2_3 off ops amd_external_pcie_gpp_ops end - device pci 02.4 alias gpp_bridge_2_4 off ops amd_external_pcie_gpp_ops end - device pci 02.5 alias gpp_bridge_2_5 off ops amd_external_pcie_gpp_ops end - device pci 02.6 alias gpp_bridge_2_6 off ops amd_external_pcie_gpp_ops end + device pci 02.1 alias gpp_bridge_2_1 hidden ops amd_external_pcie_gpp_ops end + device pci 02.2 alias gpp_bridge_2_2 hidden ops amd_external_pcie_gpp_ops end + device pci 02.3 alias gpp_bridge_2_3 hidden ops amd_external_pcie_gpp_ops end + device pci 02.4 alias gpp_bridge_2_4 hidden ops amd_external_pcie_gpp_ops end + device pci 02.5 alias gpp_bridge_2_5 hidden ops amd_external_pcie_gpp_ops end + device pci 02.6 alias gpp_bridge_2_6 hidden ops amd_external_pcie_gpp_ops end device pci 03.0 on end # Dummy Host Bridge, do not disable device pci 03.1 alias usb4_pcie_bridge_0 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/74527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b7577baa2dbb0ea7ebbcdb1a8ae81770e61d76f Gerrit-Change-Number: 74527 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/mendocino: Mark PCIe GPP bridges as hidden instead of off
by Martin L Roth (Code Review) 19 Apr '23

19 Apr '23

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74526 ) Change subject: soc/amd/mendocino: Mark PCIe GPP bridges as hidden instead of off ...................................................................... soc/amd/mendocino: Mark PCIe GPP bridges as hidden instead of off When one of the General-Purpose PCIe bridges is not used, it doesn't show up on the PCI bus at all, so coreboot notes it as an issue in the devicetree. This happens even if the device is marked as off. To solve this, we're marking the GPP bridge devices in devicetree as hidden, so they'll only show up in devicetree if they're actually used on a mainboard. BUG=None TEST=Don't see the "PCI: Leftover static devices:" warning for these in the boot console. BRANCH=skyrim Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I517776e4dedc70e957a0c836ab3c2e5d49e156d2 --- M src/soc/amd/mendocino/chipset_mendocino.cb M src/soc/amd/mendocino/chipset_rembrandt.cb 2 files changed, 32 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/74526/1 diff --git a/src/soc/amd/mendocino/chipset_mendocino.cb b/src/soc/amd/mendocino/chipset_mendocino.cb index b4efdf5..c1da13c 100644 --- a/src/soc/amd/mendocino/chipset_mendocino.cb +++ b/src/soc/amd/mendocino/chipset_mendocino.cb @@ -10,10 +10,10 @@ device pci 01.0 on end # Dummy Host Bridge device pci 02.0 on end # Dummy Host Bridge, do not disable - device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end - device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end - device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end - device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end + device pci 02.1 alias gpp_bridge_0 hidden ops amd_external_pcie_gpp_ops end + device pci 02.2 alias gpp_bridge_1 hidden ops amd_external_pcie_gpp_ops end + device pci 02.3 alias gpp_bridge_2 hidden ops amd_external_pcie_gpp_ops end + device pci 02.4 alias gpp_bridge_3 hidden ops amd_external_pcie_gpp_ops end device pci 08.0 on end # Dummy Host Bridge, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A diff --git a/src/soc/amd/mendocino/chipset_rembrandt.cb b/src/soc/amd/mendocino/chipset_rembrandt.cb index 2ecb2405..fe97cf8 100644 --- a/src/soc/amd/mendocino/chipset_rembrandt.cb +++ b/src/soc/amd/mendocino/chipset_rembrandt.cb @@ -10,12 +10,12 @@ device pci 01.0 on end # Dummy Host Bridge device pci 02.0 on end # Dummy Host Bridge, do not disable - device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end - device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end - device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end - device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end - device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end - device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end + device pci 02.1 alias gpp_bridge_0 hidden ops amd_external_pcie_gpp_ops end + device pci 02.2 alias gpp_bridge_1 hidden ops amd_external_pcie_gpp_ops end + device pci 02.3 alias gpp_bridge_2 hidden ops amd_external_pcie_gpp_ops end + device pci 02.4 alias gpp_bridge_3 hidden ops amd_external_pcie_gpp_ops end + device pci 02.5 alias gpp_bridge_4 hidden ops amd_external_pcie_gpp_ops end + device pci 02.6 alias gpp_bridge_5 hidden ops amd_external_pcie_gpp_ops end device pci 08.0 on end # Dummy Host Bridge, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A -- To view, visit https://review.coreboot.org/c/coreboot/+/74526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I517776e4dedc70e957a0c836ab3c2e5d49e156d2 Gerrit-Change-Number: 74526 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/amd/phoenix/include/soc/pci_devs: update defines to match the PPR
by Matt DeVillier (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Jason Glenesk, Fred Reitberger, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74565 ) Change subject: soc/amd/phoenix/include/soc/pci_devs: update defines to match the PPR ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9429c03839bb0199a04cd6cafe9a955ebdacc91 Gerrit-Change-Number: 74565 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 19 Apr 2023 19:35:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix/devicetree: drop i2s_ac97 device
by Matt DeVillier (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Jason Glenesk, Fred Reitberger, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74564 ) Change subject: soc/amd/phoenix/devicetree: drop i2s_ac97 device ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd115953bdd60e1dfcc79797b0c2158e5d861636 Gerrit-Change-Number: 74564 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 19 Apr 2023 19:33:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/myst: Enable PCIe devices in devicetree
by Felix Held (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Tim Van Patten. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74112 ) Change subject: mb/google/myst: Enable PCIe devices in devicetree ...................................................................... Patch Set 38: (1 comment) File src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h: https://review.coreboot.org/c/coreboot/+/74112/comment/e48264be_ac3fdb9c PS38, Line 11: PCIE_GPP_2_0_DEVFN > oh, phoenix' soc/pci_defs. […] pushed CB:74565 -- To view, visit https://review.coreboot.org/c/coreboot/+/74112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Gerrit-Change-Number: 74112 Gerrit-PatchSet: 38 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Wed, 19 Apr 2023 19:19:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/phoenix/include/soc/pci_devs: update defines to match the PPR
by Felix Held (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74565 ) Change subject: soc/amd/phoenix/include/soc/pci_devs: update defines to match the PPR ...................................................................... soc/amd/phoenix/include/soc/pci_devs: update defines to match the PPR Parts of this file were still a copy of the file from the Mendocino SoC, so update the file to match the PPR #57019 Rev 3.03 and the chipset devicetree of the Phoenix SoC. Phoenix has 4 GFX/GPP PCIe bridges/ports, the numbering scheme of the GPP PCIe bridges/ports was changed so that the numbers match the device and function numbers, and there are new device functions for the IPU and the USB4 controller and router devices. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie9429c03839bb0199a04cd6cafe9a955ebdacc91 --- M src/soc/amd/phoenix/include/soc/pci_devs.h 1 file changed, 62 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/74565/1 diff --git a/src/soc/amd/phoenix/include/soc/pci_devs.h b/src/soc/amd/phoenix/include/soc/pci_devs.h index efe84bc..0dde0ba 100644 --- a/src/soc/amd/phoenix/include/soc/pci_devs.h +++ b/src/soc/amd/phoenix/include/soc/pci_devs.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Phoenix */ - #ifndef AMD_PHOENIX_PCI_DEVS_H #define AMD_PHOENIX_PCI_DEVS_H @@ -20,36 +18,52 @@ #define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC) #define SOC_IOMMU_DEV _SOC_DEV(IOMMU_DEV, IOMMU_FUNC) -/* PCIe GFX/GPP Bridge device 1 with no ports */ +/* PCIe GFX/GPP Bridge device 1 with 4 ports */ #define PCIE_GPP_BRIDGE_1_DEV 0x1 +#define PCIE_GPP_1_1_FUNC 1 +#define PCIE_GPP_1_1_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_1_FUNC) +#define SOC_GPP_1_1_DEV _SOC_DEV(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_1_FUNC) + +#define PCIE_GPP_1_2_FUNC 2 +#define PCIE_GPP_1_2_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_2_FUNC) +#define SOC_GPP_1_2_DEV _SOC_DEV(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_2_FUNC) + +#define PCIE_GPP_1_3_FUNC 3 +#define PCIE_GPP_1_3_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_3_FUNC) +#define SOC_GPP_1_3_DEV _SOC_DEV(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_3_FUNC) + +#define PCIE_GPP_1_4_FUNC 4 +#define PCIE_GPP_1_4_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_4_FUNC) +#define SOC_GPP_1_4_DEV _SOC_DEV(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_4_FUNC) + /* PCIe GPP Bridge device 2 with up to 6 ports */ #define PCIE_GPP_BRIDGE_2_DEV 0x2 -#define PCIE_GPP_2_0_FUNC 1 -#define PCIE_GPP_2_0_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_0_FUNC) -#define SOC_GPP_2_0_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_0_FUNC) - -#define PCIE_GPP_2_1_FUNC 2 +#define PCIE_GPP_2_1_FUNC 1 #define PCIE_GPP_2_1_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_1_FUNC) #define SOC_GPP_2_1_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_1_FUNC) -#define PCIE_GPP_2_2_FUNC 3 +#define PCIE_GPP_2_2_FUNC 2 #define PCIE_GPP_2_2_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_2_FUNC) #define SOC_GPP_2_2_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_2_FUNC) -#define PCIE_GPP_2_3_FUNC 4 +#define PCIE_GPP_2_3_FUNC 3 #define PCIE_GPP_2_3_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_3_FUNC) #define SOC_GPP_2_3_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_3_FUNC) -#define PCIE_GPP_2_4_FUNC 5 +#define PCIE_GPP_2_4_FUNC 4 #define PCIE_GPP_2_4_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_4_FUNC) #define SOC_GPP_2_4_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_4_FUNC) -#define PCIE_GPP_2_5_FUNC 6 +#define PCIE_GPP_2_5_FUNC 5 #define PCIE_GPP_2_5_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_5_FUNC) #define SOC_GPP_2_5_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_5_FUNC) +#define PCIE_GPP_2_6_FUNC 6 +#define PCIE_GPP_2_6_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_6_FUNC) +#define SOC_GPP_2_6_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_6_FUNC) + /* PCIe Bridges to Bus A, Bus B and Bus C devices */ #define PCIE_ABC_BRIDGE_DEV 0x8 @@ -85,13 +99,29 @@ #define PCIE_GPP_B_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_B_FUNC) #define SOC_PCIE_GPP_B_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_B_FUNC) +#define GFX_IPU_DEV 0x0 +#define GFX_IPU_FUNC 1 +#define GFX_IPU_DEVFN PCI_DEVFN(GFX_IPU_DEV, GFX_IPU_FUNC) + #define PCIE_ABC_C_FUNC 3 #define PCIE_GPP_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define SOC_PCIE_GPP_C_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) -#define XHCI2_DEV 0x0 -#define XHCI2_FUNC 0 -#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV, XHCI2_FUNC) +#define USB4_XHCI0_DEV 0x0 +#define USB4_XHCI0_FUNC 3 +#define USB4_XHCI0_DEVFN PCI_DEVFN(USB4_XHCI0_DEV, USB4_XHCI0_FUNC) + +#define USB4_XHCI1_DEV 0x0 +#define USB4_XHCI1_FUNC 4 +#define USB4_XHCI1_DEVFN PCI_DEVFN(USB4_XHCI1_DEV, USB4_XHCI1_FUNC) + +#define USB4_ROUTER0_DEV 0x0 +#define USB4_ROUTER0_FUNC 5 +#define USB4_ROUTER0_DEVFN PCI_DEVFN(USB4_ROUTER0_DEV, USB4_ROUTER0_FUNC) + +#define USB4_ROUTER1_DEV 0x0 +#define USB4_ROUTER1_FUNC 6 +#define USB4_ROUTER1_DEVFN PCI_DEVFN(USB4_ROUTER1_DEV, USB4_ROUTER1_FUNC) /* SMBUS */ #define SMBUS_DEV 0x14 -- To view, visit https://review.coreboot.org/c/coreboot/+/74565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9429c03839bb0199a04cd6cafe9a955ebdacc91 Gerrit-Change-Number: 74565 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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