coreboot-gerrit April 2023

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[M] Change in coreboot[master]: soc/intel/meteorlake: support Power Limits and Voltage Regulator
by build bot (Jenkins) (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74572 ) Change subject: soc/intel/meteorlake: support Power Limits and Voltage Regulator ...................................................................... Patch Set 2: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174577): https://review.coreboot.org/c/coreboot/+/74572/comment/97814ed0_429e346f PS2, Line 21: Therefor, this patch adds support to apply Power Limits and Voltage 'Therefor' may be misspelled - perhaps 'Therefore'? File src/soc/intel/meteorlake/chip.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174577): https://review.coreboot.org/c/coreboot/+/74572/comment/ca54ab40_fd513513 PS2, Line 49: /* Thermal Design Current current limit. Possible repeated word: 'Current' -- To view, visit https://review.coreboot.org/c/coreboot/+/74572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1a6d4872718730951591cde6677557eebe3a944 Gerrit-Change-Number: 74572 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 19 Apr 2023 20:35:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/meteorlake: support Power Limits and Voltage Regulator
by Jérémy Compostella (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Hello Tarun Tuli, Subrata Banik, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74572 to look at the new patch set (#2). Change subject: soc/intel/meteorlake: support Power Limits and Voltage Regulator ...................................................................... soc/intel/meteorlake: support Power Limits and Voltage Regulator Power Limits and Voltage Regulator settings are the result of at least the following combination of factors: - The voltage regular itself - The TDP/SoC used - The board design (extra chips, cooling system, ...) - The Operating System and the use-cases - Power and performance measurements and tuning Those settings being board design and use-case specific, they cannot be reduced to simple database indexed on a SoC ID and TDP. They must factor in the board itself. Therefor, this patch adds support to apply Power Limits and Voltage Regulator settings supplied by a board specific database. Note that the FSP includes default Power Limits and Voltage Regulator settings. These settings may be good enough for basic board bring-up but should be refined per board design. BRANCH=None BUG=b:262499722 TEST=TBD Change-Id: Ia1a6d4872718730951591cde6677557eebe3a944 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/chipset.cb M src/soc/intel/meteorlake/romstage/fsp_params.c M src/soc/intel/meteorlake/systemagent.c 4 files changed, 135 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/74572/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1a6d4872718730951591cde6677557eebe3a944 Gerrit-Change-Number: 74572 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/meteorlake: support Power Limits and Voltage Regulator
by build bot (Jenkins) (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74572 ) Change subject: soc/intel/meteorlake: support Power Limits and Voltage Regulator ...................................................................... Patch Set 1: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174575): https://review.coreboot.org/c/coreboot/+/74572/comment/625aed17_0e8f85bf PS1, Line 21: Therefor, this patch adds support to apply Power Limits and Voltage 'Therefor' may be misspelled - perhaps 'Therefore'? File src/soc/intel/meteorlake/chip.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174575): https://review.coreboot.org/c/coreboot/+/74572/comment/5acc20b5_b0a8997e PS1, Line 49: /* Thermal Design Current current limit. Possible repeated word: 'Current' -- To view, visit https://review.coreboot.org/c/coreboot/+/74572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1a6d4872718730951591cde6677557eebe3a944 Gerrit-Change-Number: 74572 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 19 Apr 2023 20:32:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Add Power Limits
by Jérémy Compostella (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74573 ) Change subject: mb/google/rex: Add Power Limits ...................................................................... mb/google/rex: Add Power Limits This patch defines the Power Limits applicable to the rex board designs per document #640982 revision 1p1 and considering that Fast VMode is enabled. BRANCH=None BUG=b:262499722 TEST=TBD Change-Id: Id01ba17567eb072941a687a70cf13405469a5a3c Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb 1 file changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/74573/1 diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 9a71e95..08e1c40 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -1,4 +1,24 @@ chip soc/intel/meteorlake + register "power_config" = "{ + { + .sa_dev_id = PCI_DID_INTEL_MTL_P_ID_1, + .tdp = 45, + .limits = { + .tdp_pl1_override = 45, + .tdp_pl2_override = 115, + .tdp_pl4 = 197 + } + }, + { + .sa_dev_id = PCI_DID_INTEL_MTL_P_ID_2, + .tdp = 15, + .limits = { + .tdp_pl1_override = 15, + .tdp_pl2_override = 57, + .tdp_pl4 = 101 + } + } + }" # GPE configuration register "pmc_gpe0_dw0" = "GPP_B" -- To view, visit https://review.coreboot.org/c/coreboot/+/74573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id01ba17567eb072941a687a70cf13405469a5a3c Gerrit-Change-Number: 74573 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/meteorlake: support Power Limits and Voltage Regulator
by Jérémy Compostella (Code Review) 19 Apr '23

19 Apr '23

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74572 ) Change subject: soc/intel/meteorlake: support Power Limits and Voltage Regulator ...................................................................... soc/intel/meteorlake: support Power Limits and Voltage Regulator Power Limits and Voltage Regulator settings are the result of at least the following combination of factors: - The voltage regular itself - The TDP/SoC used - The board design (extra chips, cooling system, ...) - The Operating System and the use-cases - Power and performance measurements and tuning Those settings being board design and use-case specific, they cannot be reduced to simple database indexed on a SoC ID and TDP. They must factor in the board itself. Therefor, this patch adds support to apply Power Limits and Voltage Regulator settings supplied by a board specific database. Note that the FSP includes default Power Limits and Voltage Regulator settings. These settings may be good enough for basic board bring-up but should be refined per board design. BRANCH=None BUG=b:262499722 TEST=TBD Change-Id: Ia1a6d4872718730951591cde6677557eebe3a944 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/chipset.cb M src/soc/intel/meteorlake/romstage/fsp_params.c M src/soc/intel/meteorlake/systemagent.c 4 files changed, 139 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/74572/1 diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index dbe5eb1..905a14a 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -3,6 +3,7 @@ #ifndef _SOC_CHIP_H_ #define _SOC_CHIP_H_ +#include <device/pci_ids.h> #include <drivers/i2c/designware/dw_i2c.h> #include <gpio.h> #include <intelblocks/cfg.h> @@ -17,13 +18,50 @@ #include <soc/usb.h> #include <stdint.h> -/* Types of different SKUs */ -enum soc_intel_meteorlake_power_limits { - MTL_P_POWER_LIMITS_1, - MTL_P_POWER_LIMITS_2, - MTL_P_POWER_LIMITS_3, - MTL_P_POWER_LIMITS_4, - MTL_POWER_LIMITS_COUNT +#define MTL_PL_VR_COUNT 8 +#define MTL_VR_DOMAINS 2 + +/* + * Power limits and voltage regulator settings depends on: + * 1. Board design / Voltage Regulator / EC + * 2. Thermal Design Power of the System on Chip + * 3. The System on Chip + * + * These settings should be provided by the mainboard or variant override. + * + * FSP silicon sets default values taking into account #2 and #3 and based on + * Intel board design. UPD can be used to override those values. + */ +struct soc_voltage_regulator_config { + /* AC and DC Loadline. + They are in 1/100 mOhms (ie. 1250 = 12.50 mOhms) and range is 0-6249. */ + uint16_t ac_loadline; + uint16_t dc_loadline; + + /* VR Icc Max limit. + Range is from 0-255A in 1/4 A units (400 = 100A). */ + uint16_t icc_max; + + /* Thermal Design Current time window. + Defined in milli seconds and range 1ms to 448s. */ + uint32_t tdc_timewindow; + + /* Thermal Design Current current limit. + Defined in 1/8A units and range is 0-4095. 1000 = 125A. */ + uint16_t tdc_currentlimit; + + /* Power State 1/2/3 Threshold Current. + Defined in 1/4A units and range is 0-128A */ + uint16_t psi1threshold; + uint16_t psi2threshold; + uint16_t psi3threshold; +}; + +struct soc_intel_meteorlake_power_settings { + uint32_t sa_dev_id; + uint8_t tdp; + struct soc_power_limits_config limits; + struct soc_voltage_regulator_config vr[MTL_VR_DOMAINS]; }; /* Types of display ports */ @@ -81,8 +119,11 @@ /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; - /* Common struct containing power limits configuration information */ - struct soc_power_limits_config power_limits_config[MTL_POWER_LIMITS_COUNT]; + /* + * Common struct containing power limits and voltage regular + * configuration information + */ + struct soc_intel_meteorlake_power_settings power_config[MTL_PL_VR_COUNT]; /* Gpio group routed to each dword of the GPE0 block. Values are * of the form PMC_GPP_[A:U] or GPD. */ diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb index 3af284c..b711b89 100644 --- a/src/soc/intel/meteorlake/chipset.cb +++ b/src/soc/intel/meteorlake/chipset.cb @@ -2,17 +2,6 @@ device cpu_cluster 0 on end - #FIXME: update values for MTL and enable override in systemagent.c - register "power_limits_config[MTL_P_POWER_LIMITS_2]" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 55, - }" - - register "power_limits_config[MTL_P_POWER_LIMITS_1]" = "{ - .tdp_pl1_override = 45, - .tdp_pl2_override = 115, - }" - # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of # putting it under register "common_soc_config" in overridetree.cb file. diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index ec5a3af..26a6e47 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -5,6 +5,7 @@ #include <cpu/intel/cpu_ids.h> #include <cpu/x86/msr.h> #include <device/device.h> +#include <device/pci.h> #include <drivers/wifi/generic/wifi.h> #include <fsp/fsp_debug_event.h> #include <fsp/util.h> @@ -275,6 +276,40 @@ m_cfg->VmxEnable = CONFIG(ENABLE_VMX); } +static void fill_fspm_vr_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_meteorlake_config *config) +{ + uint8_t tdp; + uint16_t sa_dev_id; + const struct soc_intel_meteorlake_power_settings *cur; + + /* Get System Agent PCI ID and Thermal Design Power */ + sa_dev_id = pci_read_config16(SA_DEV_ROOT, PCI_DEVICE_ID); + tdp = get_cpu_tdp(); + + for (size_t i = 0; i < ARRAY_SIZE(config->power_config); i++) { + cur = &config->power_config[i]; + if (!cur->sa_dev_id) + break; + + if (cur->sa_dev_id != sa_dev_id || cur->tdp != tdp) + continue; + + for (size_t domain = 0; domain < ARRAY_SIZE(cur->vr); domain++) { + m_cfg->AcLoadline[domain] = cur->vr[domain].ac_loadline; + m_cfg->DcLoadline[domain] = cur->vr[domain].dc_loadline; + m_cfg->IccMax[domain] = cur->vr[domain].icc_max; + m_cfg->Psi1Threshold[domain] = cur->vr[domain].psi1threshold; + m_cfg->Psi2Threshold[domain] = cur->vr[domain].psi2threshold; + m_cfg->Psi3Threshold[domain] = cur->vr[domain].psi3threshold; + } + + return; + } + + printk(BIOS_DEBUG, "No Voltage Regular settings override found\n"); +} + static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_meteorlake_config *config) { @@ -307,6 +342,7 @@ fill_fspm_tcss_params, fill_fspm_usb4_params, fill_fspm_vtd_params, + fill_fspm_vr_params, fill_fspm_trace_params, }; diff --git a/src/soc/intel/meteorlake/systemagent.c b/src/soc/intel/meteorlake/systemagent.c index 81e4bed..d26b793 100644 --- a/src/soc/intel/meteorlake/systemagent.c +++ b/src/soc/intel/meteorlake/systemagent.c @@ -152,45 +152,41 @@ */ void soc_systemagent_init(struct device *dev) { - struct soc_power_limits_config *soc_config; struct device *sa; uint16_t sa_pci_id; + uint8_t tdp; config_t *config; + const struct soc_intel_meteorlake_power_settings *cur; /* Enable Power Aware Interrupt Routing */ enable_power_aware_intr(); config = config_of_soc(); - /* Get System Agent PCI ID */ + /* Get System Agent PCI ID and TDP */ sa = pcidev_path_on_root(PCI_DEVFN_ROOT); - sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF; + if (!sa) + return; + sa_pci_id = pci_read_config16(sa, PCI_DEVICE_ID); + tdp = get_cpu_tdp(); /* Choose a power limits configuration based on the SoC SKU type, * differentiated here based on SA PCI ID. */ - switch (sa_pci_id) { - case PCI_DID_INTEL_MTL_P_ID_1: - soc_config = &config->power_limits_config[MTL_P_POWER_LIMITS_1]; - break; - case PCI_DID_INTEL_MTL_P_ID_2: - soc_config = &config->power_limits_config[MTL_P_POWER_LIMITS_2]; - break; - case PCI_DID_INTEL_MTL_P_ID_3: - soc_config = &config->power_limits_config[MTL_P_POWER_LIMITS_3]; - break; - case PCI_DID_INTEL_MTL_P_ID_4: - soc_config = &config->power_limits_config[MTL_P_POWER_LIMITS_4]; - break; - default: - printk(BIOS_ERR, "unknown SA ID: 0x%4x, skipping power limits configuration\n", - sa_pci_id); + for (size_t i = 0; i < ARRAY_SIZE(config->power_config); i++) { + cur = &config->power_config[i]; + if (!cur->sa_dev_id) + break; + + if (cur->sa_dev_id != sa_pci_id || cur->tdp != tdp) + continue; + + /* TODO: `set_power_limits()' should take a `const struct + soc_power_limits_config *'. Fix `set_power_limits()' instead + of casting here. */ + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, + (struct soc_power_limits_config *)&cur->limits); return; } - - /* Remove once commented line below is enabled */ - (void)soc_config; - /* UPDATEME: Need to enable later */ - //set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); } uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) -- To view, visit https://review.coreboot.org/c/coreboot/+/74572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1a6d4872718730951591cde6677557eebe3a944 Gerrit-Change-Number: 74572 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/amd/phoenix/include/soc/pci_devs: update defines to match the PPR
by Raul Rangel (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Jason Glenesk, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74565 ) Change subject: soc/amd/phoenix/include/soc/pci_devs: update defines to match the PPR ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/soc/amd/phoenix/include/soc/pci_devs.h: https://review.coreboot.org/c/coreboot/+/74565/comment/b33c62fc_ea2097ce PS1, Line 43: PCIE_GPP_2_1_FUNC Thanks for making 1 = 1, the 0 = 1 was always very confusing. -- To view, visit https://review.coreboot.org/c/coreboot/+/74565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9429c03839bb0199a04cd6cafe9a955ebdacc91 Gerrit-Change-Number: 74565 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 19 Apr 2023 20:28:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: [WIP] ACPI: Add usb_charge_mode_from_gnvs()
by Kyösti Mälkki (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Lance Zhao, Caveh Jalali, Tim Wawrzynczak, Kyösti Mälkki, Boris Mittelberg. Hello Lance Zhao, build bot (Jenkins), Caveh Jalali, Tim Wawrzynczak, Boris Mittelberg, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74524 to look at the new patch set (#3). Change subject: [WIP] ACPI: Add usb_charge_mode_from_gnvs() ...................................................................... [WIP] ACPI: Add usb_charge_mode_from_gnvs() Used together with (old API?) of ChromeEC to control USB port power for S3/S4/S5 sleep states. Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/acpi_pm.c M src/ec/google/chromeec/smihandler.c M src/ec/google/chromeec/smm.h M src/include/acpi/acpi_gnvs.h M src/mainboard/google/auron/smihandler.c M src/mainboard/google/butterfly/smihandler.c M src/mainboard/google/cyan/smihandler.c M src/mainboard/google/link/smihandler.c M src/mainboard/google/parrot/smihandler.c M src/mainboard/google/rambi/smihandler.c M src/mainboard/google/slippy/smihandler.c M src/mainboard/google/stout/smihandler.c M src/mainboard/intel/strago/smihandler.c M src/soc/intel/broadwell/include/soc/nvs.h 14 files changed, 107 insertions(+), 100 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/74524/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9 Gerrit-Change-Number: 74524 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: [WIP] ACPI: Add usb_charge_mode_from_gnvs()
by Kyösti Mälkki (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Lance Zhao, Caveh Jalali, Tim Wawrzynczak, Kyösti Mälkki, Boris Mittelberg. Hello Lance Zhao, build bot (Jenkins), Caveh Jalali, Tim Wawrzynczak, Boris Mittelberg, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74524 to look at the new patch set (#2). Change subject: [WIP] ACPI: Add usb_charge_mode_from_gnvs() ...................................................................... [WIP] ACPI: Add usb_charge_mode_from_gnvs() Used together with (old API?) of ChromeEC to control USB port power for S3/S4/S5 sleep states. Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/acpi_pm.c M src/ec/google/chromeec/smihandler.c M src/ec/google/chromeec/smm.h M src/include/acpi/acpi_gnvs.h M src/mainboard/google/auron/smihandler.c M src/mainboard/google/butterfly/smihandler.c M src/mainboard/google/cyan/smihandler.c M src/mainboard/google/link/smihandler.c M src/mainboard/google/parrot/smihandler.c M src/mainboard/google/rambi/smihandler.c M src/mainboard/google/slippy/smihandler.c M src/mainboard/google/stout/smihandler.c M src/mainboard/intel/strago/smihandler.c 13 files changed, 104 insertions(+), 99 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/74524/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9 Gerrit-Change-Number: 74524 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/amd/mayan/port_descriptors.c: Update DXIO for mayan
by Fred Reitberger (Code Review) 19 Apr '23

19 Apr '23

Fred Reitberger has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/70214 ) Change subject: mb/amd/mayan/port_descriptors.c: Update DXIO for mayan ...................................................................... Abandoned CB:74191 is covering this -- To view, visit https://review.coreboot.org/c/coreboot/+/70214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1aca5423879433c1d0d2405d96cf7d806c57b20 Gerrit-Change-Number: 70214 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: soc/amd/phoenix/xhci: Correct counting of xhci_sci_sources
by Felix Held (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74528 ) Change subject: soc/amd/phoenix/xhci: Correct counting of xhci_sci_sources ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: good catch -- To view, visit https://review.coreboot.org/c/coreboot/+/74528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabba97e003d1a5140c98e3fc5a3496f66f8795c2 Gerrit-Change-Number: 74528 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 19 Apr 2023 20:08:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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