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Change subject: mb/google/rex: Add RTD3 support for SSD
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> Can you please check the S0ix is working w/ this CL?
We will validate and let you know.
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Change subject: soc/intel/meteorlake: Enable Key Locker
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Patch Set 21:
(1 comment)
Patchset:
PS21:
> 20ms boot time regression seen.
The data Pratik has added in commit message is from CPFE 15415.0.0 and with or without this patch.
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Change subject: soc/amd/stoneyridge/northbridge: fix indentation in set_mmio_addr_reg
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Patch Set 1: Code-Review+1
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Change subject: soc/amd/phoenix/include/soc/pci_devs: update defines to match the PPR
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Patch Set 1:
(1 comment)
File src/soc/amd/phoenix/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/74565/comment/3563ce2c_2827dcdd
PS1, Line 43: PCIE_GPP_2_1_FUNC
> Thanks for making 1 = 1, the 0 = 1 was always very confusing.
the gpp bridge number always was off by one in the ppr; since we now have bridges on both device 1 and device 2, we moved over to using the device and function numbers
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