coreboot-gerrit April 2023

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[M] Change in coreboot[master]: soc/intel/meteorlake: support Power Limits and Voltage Regulator
by Jérémy Compostella (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Sumeet R Pawnikar. Hello Tarun Tuli, Subrata Banik, Kapil Porwal, Sumeet R Pawnikar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74572 to look at the new patch set (#5). Change subject: soc/intel/meteorlake: support Power Limits and Voltage Regulator ...................................................................... soc/intel/meteorlake: support Power Limits and Voltage Regulator Power Limits and Voltage Regulator settings are the result of at least the following combination of factors: - The voltage regular itself - The TDP/SoC used - The board design (extra chips, cooling system, ...) - The Operating System and the use-cases - Power and performance measurements and tuning Those settings being board design and use-case specific, they cannot be reduced to simple database indexed on a SoC ID and TDP. They must factor in the board itself. Therefore, this patch adds support to apply Power Limits and Voltage Regulator settings supplied by a board specific database. Note that the FSP includes default Power Limits and Voltage Regulator settings. These settings may be good enough for basic board bring-up but should be refined per board design. BRANCH=None BUG=b:262499722 TEST=Using `iotools rdmsr 0 0x610' and `iotools rdmsr 0 0x601', we verified that PL1, PL2 and PL4 settings are applied on 15W Rex board Change-Id: Ia1a6d4872718730951591cde6677557eebe3a944 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/chipset.cb M src/soc/intel/meteorlake/romstage/fsp_params.c M src/soc/intel/meteorlake/systemagent.c 4 files changed, 173 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/74572/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/74572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1a6d4872718730951591cde6677557eebe3a944 Gerrit-Change-Number: 74572 Gerrit-PatchSet: 5 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: mb/amd/birman/ec.c: Update EC configuration
by Felix Held (Code Review) 20 Apr '23

20 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73971 ) Change subject: mb/amd/birman/ec.c: Update EC configuration ...................................................................... mb/amd/birman/ec.c: Update EC configuration Update the EC GPIO values for Birman, per schematic # 105-D67000-00B Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: Icd9df120f555eb06f920f6263a8d2ab45c05baec Reviewed-on: https://review.coreboot.org/c/coreboot/+/73971 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/amd/birman/Kconfig M src/mainboard/amd/birman/ec.c 2 files changed, 231 insertions(+), 25 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/amd/birman/Kconfig b/src/mainboard/amd/birman/Kconfig index 7fa541c..d27c38b 100644 --- a/src/mainboard/amd/birman/Kconfig +++ b/src/mainboard/amd/birman/Kconfig @@ -76,6 +76,51 @@ # We don't have recovery buttons, so we can't manually enable devmode. select GBB_FLAG_FORCE_DEV_SWITCH_ON +config ENABLE_EVAL_CARD + bool "Enable Eval Card" + help + Enable the Eval Card PCIe slot + +config ENABLE_EVAL_19V + bool "Enable 19V rail for Eval Card" + depends on ENABLE_EVAL_CARD + help + Enable the 19V rail for Eval Card PCIe slot + +choice + prompt "DT SLOT/M.2 SSD1 ENABLE" + default ENABLE_DT_SLOT + help + Either DT slot or M.2 SSD1 can be used, as they are sharing PCIe lanes. + +config ENABLE_DT_SLOT + bool "Enable DT slot" + +config ENABLE_M2_SSD1 + bool "Enable M.2 SSD1" + +config DISABLE_DT_M2 + bool "Disable both DT and M.2 slot" + +endchoice + +choice + prompt "WLAN/WWAN Selection" + default WLAN0_WWAN0 + help + WLAN and WWAN lane configuration + +config WLAN0_WWAN0 + bool "Both WLAN and WWAN Enabled (1 lane each)" + +config WLAN01 + bool "Only WLAN Enabled (2 lanes WLAN, 0 lanes WWAN)" + +config WWAN01 + bool "Only WWAN Enabled (2 lanes WWAN, 0 lanes WLAN)" + +endchoice + if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig config EFS_SPI_READ_MODE default 3 # Quad IO (1-1-4) diff --git a/src/mainboard/amd/birman/ec.c b/src/mainboard/amd/birman/ec.c index 3775ef5..6646aa9 100644 --- a/src/mainboard/amd/birman/ec.c +++ b/src/mainboard/amd/birman/ec.c @@ -1,63 +1,209 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for birman */ - +#include <console/console.h> #include <ec/acpi/ec.h> +#include <stdint.h> #include "ec.h" -#define BIRMAN_EC_CMD 0x666 -#define BIRMAN_EC_DATA 0x662 +#define BIRMAN_EC_CMD 0x666 +#define BIRMAN_EC_DATA 0x662 + +#define EC_GPIO_1_ADDR 0xA1 +#define EC1_EVAL_PWREN BIT(1) + +#define EC_GPIO_2_ADDR 0xA2 +#define EC2_EVAL_SLOT_PWREN BIT(5) +#define EC2_EVAL_19V_EN BIT(2) #define EC_GPIO_3_ADDR 0xA3 -#define EC_GPIO_LOM_RESET_AUX BIT(1) +#define EC3_WLAN_RST_AUX BIT(5) +#define EC3_WWAN_RST_AUX BIT(4) +#define EC3_SD_RST_AUX BIT(3) +#define EC3_DT_RST_AUX BIT(2) +#define EC3_LOM_RST_AUX BIT(1) +#define EC3_EVAL_RST_AUX BIT(0) #define EC_GPIO_7_ADDR 0xA7 -#define EC_GPIO_DT_PWREN BIT(2) -#define EC_GPIO_WWAN_MODULE_RST BIT(5) +#define EC7_WWAN_PWR_OFF_N BIT(7) +#define EC7_BT_RADIO_DIS BIT(2) +#define EC7_WL_RADIO_DIS BIT(0) #define EC_GPIO_8_ADDR 0xA8 -#define EC_GPIO_SMBUS0_EN BIT(0) +#define EC8_ADAPTER_OFF BIT(5) +#define EC8_EVAL_SMBUS1_N_SW BIT(3) +#define EC8_MP2_SEL BIT(2) +#define EC8_DT_N_SSD1_SW BIT(1) + +#define EC_GPIO_9_ADDR 0xA9 +#define EC9_CAM0_PWR_EN BIT(7) +#define EC9_CAM1_PWR_EN BIT(6) +#define EC9_WWAN_RST BIT(5) +#define EC9_DT_PWREN BIT(2) +#define EC9_TPM_PWR_EN BIT(1) +#define EC9_TPM_S0I3_N BIT(0) #define EC_GPIO_A_ADDR 0xAA -#define EC_GPIO_WWAN_PWREN BIT(3) -#define EC_GPIO_M2_SSD0_PWREN BIT(6) -#define EC_GPIO_LOM_PWREN BIT(7) +#define ECA_MUX2_S0 BIT(7) +#define ECA_MUX2_S1 BIT(6) +#define ECA_MUX1_S0 BIT(5) +#define ECA_MUX1_S1 BIT(4) +#define ECA_MUX0_S0 BIT(3) +#define ECA_MUX0_S1 BIT(2) +#define ECA_SMBUS1_EN BIT(1) +#define ECA_SMBUS0_EN BIT(0) #define EC_GPIO_C_ADDR 0xAC -#define EC_GPIO_DT_N_WLAN_SW BIT(1) -#define EC_GPIO_MP2_SEL BIT(2) -#define EC_GPIO_WWAN_N_LOM_SW BIT(3) +#define ECC_TPNL_BUF_EN BIT(6) +#define ECC_TPAD_BUF_EN BIT(5) +#define ECC_NFC_BUF_EN BIT(4) -#define EC_SW02_ADDR 0xB7 -#define EC_SW02_MS BIT(7) +#define EC_GPIO_D_ADDR 0xAD +#define ECD_TPNL_PWR_EN BIT(7) +#define ECD_TPNL_EN BIT(6) +#define ECD_SSD1_PWR_EN BIT(5) +#define ECD_FPR_PWR_EN BIT(3) +#define ECD_FPR_OFF_N BIT(2) +#define ECD_FPR_LOCK_N BIT(1) +#define ECD_TPAD_DISABLE_N BIT(0) + +#define EC_GPIO_E_ADDR 0xAE +#define ECE_LOM_PWR_EN BIT(7) +#define ECE_SSD0_PWR_EN BIT(6) +#define ECE_SD_PWR_EN BIT(5) +#define ECE_WLAN_PWR_EN BIT(4) +#define ECE_WWAN_PWR_EN BIT(3) +#define ECE_CAM_PWR_EN BIT(2) +#define ECE_FPR_N_GBE_SEL BIT(1) +#define ECE_BT_N_TPNL_SEL BIT(0) + +#define EC_GPIO_F_ADDR 0xAF +#define ECF_CAM_FW_WP_N BIT(7) +#define ECF_I2C_MUX_OE_N BIT(4) +#define ECF_WLAN0_N_WWAN1_SW BIT(1) +#define ECF_WWAN0_N_WLAN1_SW BIT(0) + +#define EC_GPIO_G_ADDR 0xB0 +#define ECG_IR_LED_PWR_EN BIT(7) +#define ECG_U0_WLAN_HDR_SEL BIT(6) +#define ECG_DT_SSD1_MUX_OFF BIT(5) +#define ECG_WLAN_WWAN_MUX_OFF BIT(4) static void configure_ec_gpio(void) { uint8_t tmp; + tmp = ec_read(EC_GPIO_1_ADDR); + if (CONFIG(ENABLE_EVAL_CARD)) { + tmp |= EC1_EVAL_PWREN; + } else { + tmp &= ~EC1_EVAL_PWREN; + } + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_1_ADDR, tmp); + ec_write(EC_GPIO_1_ADDR, tmp); + + tmp = ec_read(EC_GPIO_2_ADDR); + if (CONFIG(ENABLE_EVAL_CARD)) { + tmp |= EC2_EVAL_SLOT_PWREN; + if (CONFIG(ENABLE_EVAL_19V)) { + tmp |= EC2_EVAL_19V_EN; + } else { + tmp &= ~EC2_EVAL_19V_EN; + } + } else { + tmp &= ~EC2_EVAL_SLOT_PWREN; + tmp &= ~EC2_EVAL_19V_EN; + } + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_2_ADDR, tmp); + ec_write(EC_GPIO_2_ADDR, tmp); + tmp = ec_read(EC_GPIO_3_ADDR); - tmp |= EC_GPIO_LOM_RESET_AUX; + tmp |= EC3_WLAN_RST_AUX | EC3_WWAN_RST_AUX | EC3_SD_RST_AUX; + tmp |= EC3_DT_RST_AUX | EC3_LOM_RST_AUX | EC3_EVAL_RST_AUX; + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_3_ADDR, tmp); ec_write(EC_GPIO_3_ADDR, tmp); tmp = ec_read(EC_GPIO_7_ADDR); - tmp |= EC_GPIO_WWAN_MODULE_RST | EC_GPIO_DT_PWREN; + tmp &= ~EC7_BT_RADIO_DIS; + tmp &= ~EC7_WL_RADIO_DIS; + tmp |= EC7_WWAN_PWR_OFF_N; + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_7_ADDR, tmp); ec_write(EC_GPIO_7_ADDR, tmp); tmp = ec_read(EC_GPIO_8_ADDR); - tmp |= EC_GPIO_SMBUS0_EN; + if (CONFIG(ENABLE_M2_SSD1)) { + tmp |= EC8_DT_N_SSD1_SW; + } else { + tmp &= ~EC8_DT_N_SSD1_SW; + } + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_8_ADDR, tmp); ec_write(EC_GPIO_8_ADDR, tmp); - tmp = ec_read(EC_GPIO_A_ADDR); - tmp |= EC_GPIO_M2_SSD0_PWREN | EC_GPIO_LOM_PWREN | EC_GPIO_WWAN_PWREN; + tmp = ec_read(EC_GPIO_9_ADDR); + tmp |= EC9_CAM0_PWR_EN | EC9_CAM1_PWR_EN | EC9_WWAN_RST | EC9_TPM_PWR_EN; + if (CONFIG(ENABLE_DT_SLOT)) { + tmp |= EC9_DT_PWREN; + } else { + tmp &= ~EC9_DT_PWREN; + } + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_9_ADDR, tmp); + ec_write(EC_GPIO_9_ADDR, tmp); + + tmp = ECA_MUX1_S0 | ECA_SMBUS1_EN | ECA_SMBUS0_EN; + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_A_ADDR, tmp); ec_write(EC_GPIO_A_ADDR, tmp); tmp = ec_read(EC_GPIO_C_ADDR); - tmp |= EC_GPIO_WWAN_N_LOM_SW | EC_GPIO_MP2_SEL | EC_GPIO_DT_N_WLAN_SW; + tmp |= ECC_TPNL_BUF_EN | ECC_TPAD_BUF_EN | ECC_NFC_BUF_EN; + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_C_ADDR, tmp); ec_write(EC_GPIO_C_ADDR, tmp); - tmp = ec_read(EC_SW02_ADDR); - tmp |= EC_SW02_MS; - ec_write(EC_SW02_ADDR, tmp); + tmp = ec_read(EC_GPIO_D_ADDR); + tmp |= ECD_TPNL_PWR_EN | ECD_TPNL_EN | ECD_TPAD_DISABLE_N; + if (CONFIG(ENABLE_M2_SSD1)) { + tmp |= ECD_SSD1_PWR_EN; + } else { + tmp &= ~ECD_SSD1_PWR_EN; + } + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_D_ADDR, tmp); + ec_write(EC_GPIO_D_ADDR, tmp); + + tmp = ec_read(EC_GPIO_E_ADDR); + tmp |= ECE_LOM_PWR_EN | ECE_SSD0_PWR_EN | ECE_SD_PWR_EN; + tmp |= ECE_CAM_PWR_EN | ECE_FPR_N_GBE_SEL; + tmp &= ~ECE_BT_N_TPNL_SEL; + if (CONFIG(WLAN01)) { // no WWAN, turn off WWAN power + tmp &= ~ECE_WWAN_PWR_EN; + } else { + tmp |= ECE_WWAN_PWR_EN; + } + if (CONFIG(WWAN01)) { // no WLAN, turn off WLAN power + tmp &= ~ECE_WLAN_PWR_EN; + } else { + tmp |= ECE_WLAN_PWR_EN; + } + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_E_ADDR, tmp); + ec_write(EC_GPIO_E_ADDR, tmp); + + tmp = ec_read(EC_GPIO_F_ADDR); + if (CONFIG(WLAN01)) { + tmp |= ECF_WWAN0_N_WLAN1_SW; + } else { + tmp &= ~ECF_WWAN0_N_WLAN1_SW; + } + if (CONFIG(WWAN01)) { + tmp |= ECF_WLAN0_N_WWAN1_SW; + } else { + tmp &= ~ECF_WLAN0_N_WWAN1_SW; + } + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_F_ADDR, tmp); + ec_write(EC_GPIO_F_ADDR, tmp); + + tmp = ec_read(EC_GPIO_G_ADDR); + tmp &= ~ECG_DT_SSD1_MUX_OFF; + tmp &= ~ECG_WLAN_WWAN_MUX_OFF; + tmp |= ECG_IR_LED_PWR_EN | ECG_U0_WLAN_HDR_SEL; + printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_G_ADDR, tmp); + ec_write(EC_GPIO_G_ADDR, tmp); } void birman_ec_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/73971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd9df120f555eb06f920f6263a8d2ab45c05baec Gerrit-Change-Number: 73971 Gerrit-PatchSet: 12 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/myst: Add initial fch irq routing
by Felix Held (Code Review) 19 Apr '23

19 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74109 ) ( 29 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/myst: Add initial fch irq routing ...................................................................... mb/google/myst: Add initial fch irq routing Add initial fch irq routing table for Myst. BUG=b:275946702 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: Ic81c3cbfbb30a0beb3c4083624cf19abe6d1e694 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74109 Reviewed-by: Tim Van Patten <timvp(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/myst/mainboard.c 1 file changed, 59 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Tim Van Patten: Looks good to me, but someone else must approve Eric Lai: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/myst/mainboard.c b/src/mainboard/google/myst/mainboard.c index e433c98..3a25e8c 100644 --- a/src/mainboard/google/myst/mainboard.c +++ b/src/mainboard/google/myst/mainboard.c @@ -5,10 +5,48 @@ #include <baseboard/variants.h> #include <console/console.h> #include <device/device.h> +#include <soc/acpi.h> #include <variant/ec.h> +/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is + accessed via I/O ports 0xc00/0xc01. */ + +/* + * This controls the device -> IRQ routing. + * + * Hardcoded IRQs: + * 0: timer < soc/amd/common/acpi/lpc.asl + * 1: i8042 - Keyboard + * 2: cascade + * 8: rtc0 <- soc/amd/common/acpi/lpc.asl + * 9: acpi <- soc/amd/common/acpi/lpc.asl + */ + static const struct fch_irq_routing fch_irq_map[] = { - { 0, 0x00, 0x00 }, + { PIRQ_A, 12, PIRQ_NC }, + { PIRQ_B, 14, PIRQ_NC }, + { PIRQ_C, 15, PIRQ_NC }, + { PIRQ_D, 12, PIRQ_NC }, + { PIRQ_E, 14, PIRQ_NC }, + { PIRQ_F, 15, PIRQ_NC }, + { PIRQ_G, 12, PIRQ_NC }, + { PIRQ_H, 14, PIRQ_NC }, + + { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ }, + { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPIO, 11, 11 }, + { PIRQ_I2C0, 10, 10 }, + { PIRQ_I2C1, 7, 7 }, + { PIRQ_I2C2, 6, 6 }, + { PIRQ_I2C3, 5, 5 }, + { PIRQ_UART0, 4, 4 }, + { PIRQ_UART1, 3, 3 }, + + /* The MISC registers are not interrupt numbers */ + { PIRQ_MISC, 0xfa, 0x00 }, + { PIRQ_MISC0, 0x91, 0x00 }, + { PIRQ_HPET_L, 0x00, 0x00 }, + { PIRQ_HPET_H, 0x00, 0x00 }, }; const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) -- To view, visit https://review.coreboot.org/c/coreboot/+/74109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic81c3cbfbb30a0beb3c4083624cf19abe6d1e694 Gerrit-Change-Number: 74109 Gerrit-PatchSet: 32 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/myst: Enable PCIe devices in devicetree
by Jon Murphy (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Tim Van Patten, Felix Held. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74112 ) Change subject: mb/google/myst: Enable PCIe devices in devicetree ...................................................................... Patch Set 39: (1 comment) File src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h: https://review.coreboot.org/c/coreboot/+/74112/comment/7a6e7eb0_bc05a39b PS39, Line 10: /* PCIE_GPP_x_y_DEVFN macros are off by one*/ > with CB:74565 this is no longer true Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Gerrit-Change-Number: 74112 Gerrit-PatchSet: 39 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 19 Apr 2023 21:49:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/myst: Enable PCIe devices in devicetree
by Jon Murphy (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Tim Van Patten. Hello build bot (Jenkins), Raul Rangel, Martin L Roth, Tim Van Patten, Karthik Ramasubramanian, Felix Held, Mark Hasemeyer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74112 to look at the new patch set (#40). Change subject: mb/google/myst: Enable PCIe devices in devicetree ...................................................................... mb/google/myst: Enable PCIe devices in devicetree Ensure that DXIO descriptors are updated using info from AMD and Myst board schematics. BUG=b:275960920,b:276744321 TEST=builds Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M src/mainboard/google/myst/port_descriptors.c M src/mainboard/google/myst/variants/baseboard/devicetree.cb M src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h 3 files changed, 122 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/74112/40 -- To view, visit https://review.coreboot.org/c/coreboot/+/74112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Gerrit-Change-Number: 74112 Gerrit-PatchSet: 40 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/myst: Enable PCIe devices in devicetree
by Felix Held (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Tim Van Patten. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74112 ) Change subject: mb/google/myst: Enable PCIe devices in devicetree ...................................................................... Patch Set 39: (2 comments) File src/mainboard/google/myst/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/74112/comment/56081bd9_e3990be5 PS38, Line 51: .link_speed_capability = GEN3, using GEN_MAX should also give you gen 4 speed btw File src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h: https://review.coreboot.org/c/coreboot/+/74112/comment/95ef4265_3c6d5618 PS39, Line 10: /* PCIE_GPP_x_y_DEVFN macros are off by one*/ with CB:74565 this is no longer true -- To view, visit https://review.coreboot.org/c/coreboot/+/74112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Gerrit-Change-Number: 74112 Gerrit-PatchSet: 39 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Wed, 19 Apr 2023 21:42:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Add Power Limits
by Jérémy Compostella (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Jérémy Compostella, Kapil Porwal, Sumeet R Pawnikar. Hello Tarun Tuli, Subrata Banik, Paul Menzel, Kapil Porwal, Sumeet R Pawnikar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74573 to look at the new patch set (#4). Change subject: mb/google/rex: Add Power Limits ...................................................................... mb/google/rex: Add Power Limits This patch defines the Power Limits applicable to the rex board designs per document #640982 revision 1p1 and considering that Fast VMode is enabled. BRANCH=None BUG=b:262499722 TEST=Using `iotools rdmsr 0 0x610' and `iotools rdmsr 0 0x601', we verified that PL1, PL2 and PL4 settings are applied on 15W Rex board Change-Id: Id01ba17567eb072941a687a70cf13405469a5a3c Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb 1 file changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/74573/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id01ba17567eb072941a687a70cf13405469a5a3c Gerrit-Change-Number: 74573 Gerrit-PatchSet: 4 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/meteorlake: support Power Limits and Voltage Regulator
by Jérémy Compostella (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Sumeet R Pawnikar. Hello Tarun Tuli, Subrata Banik, Kapil Porwal, Sumeet R Pawnikar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74572 to look at the new patch set (#4). Change subject: soc/intel/meteorlake: support Power Limits and Voltage Regulator ...................................................................... soc/intel/meteorlake: support Power Limits and Voltage Regulator Power Limits and Voltage Regulator settings are the result of at least the following combination of factors: - The voltage regular itself - The TDP/SoC used - The board design (extra chips, cooling system, ...) - The Operating System and the use-cases - Power and performance measurements and tuning Those settings being board design and use-case specific, they cannot be reduced to simple database indexed on a SoC ID and TDP. They must factor in the board itself. Therefore, this patch adds support to apply Power Limits and Voltage Regulator settings supplied by a board specific database. Note that the FSP includes default Power Limits and Voltage Regulator settings. These settings may be good enough for basic board bring-up but should be refined per board design. BRANCH=None BUG=b:262499722 TEST=Using `iotools rdmsr 0 0x610' and `iotools rdmsr 0 0x601', we verified that PL1, PL2 and PL4 settings are applied on 15W Rex board Change-Id: Ia1a6d4872718730951591cde6677557eebe3a944 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/chipset.cb M src/soc/intel/meteorlake/romstage/fsp_params.c M src/soc/intel/meteorlake/systemagent.c 4 files changed, 155 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/74572/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1a6d4872718730951591cde6677557eebe3a944 Gerrit-Change-Number: 74572 Gerrit-PatchSet: 4 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/phoenix: Add note clarifying the eMMC controller
by Felix Held (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Jason Glenesk, Martin L Roth, Matt DeVillier, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74590 ) Change subject: soc/amd/phoenix: Add note clarifying the eMMC controller ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: uh oh... -- To view, visit https://review.coreboot.org/c/coreboot/+/74590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5ffd9792cbdc174d9eab7aa14d1bd6b89e1c817 Gerrit-Change-Number: 74590 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 19 Apr 2023 21:26:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix: Add note clarifying the eMMC controller
by Martin L Roth (Code Review) 19 Apr '23

19 Apr '23

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74590 ) Change subject: soc/amd/phoenix: Add note clarifying the eMMC controller ...................................................................... soc/amd/phoenix: Add note clarifying the eMMC controller The eMMC controller is present in the silicon, and is documented in the PPR, but is seemingly not bonded out on any of the existing sockets. Note this, and recommend that the controller be left disabled. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ie5ffd9792cbdc174d9eab7aa14d1bd6b89e1c817 --- M src/soc/amd/phoenix/chipset.cb 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/74590/1 diff --git a/src/soc/amd/phoenix/chipset.cb b/src/soc/amd/phoenix/chipset.cb index 606a7ce..6b1cced 100644 --- a/src/soc/amd/phoenix/chipset.cb +++ b/src/soc/amd/phoenix/chipset.cb @@ -144,5 +144,8 @@ device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end + # The eMMC controller is present on Phoenix but is not currently noted + # as being bonded out on any socket. It's included here because it's + # in the PPR, but should probably not be enabled. device mmio 0xfedd5000 alias emmc off ops amd_emmc_mmio_ops end end -- To view, visit https://review.coreboot.org/c/coreboot/+/74590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5ffd9792cbdc174d9eab7aa14d1bd6b89e1c817 Gerrit-Change-Number: 74590 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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