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Change subject: Revert "soc/amd/morgana: Remove emmc select"
......................................................................
Patch Set 1: Code-Review+2
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Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74529 )
Change subject: Revert "soc/amd/morgana: Remove emmc select"
......................................................................
Revert "soc/amd/morgana: Remove emmc select"
This reverts commit 694ef4431b127f6b1d22616a2aa1760746cbc162.
The eMMC controller is in the latest PPR (Rev3.03 - Mar 9, 2023), so add
it back into the devicetree and Kconfig.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: I84f16f27886ca866e5ac3c5a06ee1e32df617d32
---
M src/soc/amd/phoenix/Kconfig
M src/soc/amd/phoenix/chipset.cb
2 files changed, 17 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/74529/1
diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig
index 5d3adec..901b31d 100644
--- a/src/soc/amd/phoenix/Kconfig
+++ b/src/soc/amd/phoenix/Kconfig
@@ -46,6 +46,7 @@
select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
+ select SOC_AMD_COMMON_BLOCK_EMMC
select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES
select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_HAS_ESPI
diff --git a/src/soc/amd/phoenix/chipset.cb b/src/soc/amd/phoenix/chipset.cb
index 1e1ad14..606a7ce 100644
--- a/src/soc/amd/phoenix/chipset.cb
+++ b/src/soc/amd/phoenix/chipset.cb
@@ -144,4 +144,5 @@
device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end
device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end
device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end
+ device mmio 0xfedd5000 alias emmc off ops amd_emmc_mmio_ops end
end
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Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74380 )
Change subject: soc/intel/meteoerlake: set power limits dynamically
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/meteorlake/chip.h:
https://review.coreboot.org/c/coreboot/+/74380/comment/a1188a47_78178ea4
PS4, Line 38: { PCI_DID_INTEL_MTL_P_ID_2, MTL_P_282_CORE, TDP_15W },
To my understanding, this database is board specific. It points to settings which are the result of fine tuning factoring information such as the used Voltage Regulator, the particular SoC (number of E-core / P-core), TDP, the overall board design (chips, cooling, ...) along with Power and Performance measurements and tuning on this board design to meet some particular use-cases.
As a result, this database should not be in `soc/intel/meteorlake` but should be somewhere in `mainboard/`.
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Change subject: soc/intel/meteoerlake: set power limits dynamically
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> > Cf. https://partnerissuetracker.corp.google.com/issues/262499722 comment#16 […]
You are correct, this link is a bit unfair as it is private. So instead I uploaded the patch I had in progress instead (cf. https://review.coreboot.org/c/coreboot/+/74572).
I think this is a more appropriate implementation as put the board specific data into the right location.
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Hello build bot (Jenkins), Nico Huber, Tarun Tuli, Subrata Banik, Kapil Porwal, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74478
to look at the new patch set (#4).
Change subject: soc/intel/meteorlake: Replace TcssD3ColdDisable with D3COLD_SUPPORT
......................................................................
soc/intel/meteorlake: Replace TcssD3ColdDisable with D3COLD_SUPPORT
Remove the `TcssD3ColdDisable` option in devicetree, as it exists
in Kconfig. The setting is currently unused.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I08930ef84438140a13df74900570b126088bd1cb
---
M src/soc/intel/meteorlake/chip.h
M src/soc/intel/meteorlake/fsp_params.c
2 files changed, 14 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/74478/4
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