coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/amd/phoenix/devicetree: drop i2s_ac97 device
by Felix Held (Code Review) 19 Apr '23

19 Apr '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74564 ) Change subject: soc/amd/phoenix/devicetree: drop i2s_ac97 device ...................................................................... soc/amd/phoenix/devicetree: drop i2s_ac97 device In both PPR #57019 Rev 3.03 and PPR #57396 Rev 3.04, the i2s_ac97 function on bus C isn't mentioned any more and the microarchitecture specification document for this SoC also doesn't mention it, so remove it from the devicetree. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ibd115953bdd60e1dfcc79797b0c2158e5d861636 --- M src/soc/amd/phoenix/chipset.cb 1 file changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/74564/1 diff --git a/src/soc/amd/phoenix/chipset.cb b/src/soc/amd/phoenix/chipset.cb index 2d92f14..055e125 100644 --- a/src/soc/amd/phoenix/chipset.cb +++ b/src/soc/amd/phoenix/chipset.cb @@ -91,7 +91,6 @@ device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C ops amd_internal_pcie_gpp_ops device pci 0.0 on end # dummy, do not disable - device pci 0.2 alias i2s_ac97 off end device pci 0.3 alias usb4_xhci_0 off chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" -- To view, visit https://review.coreboot.org/c/coreboot/+/74564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd115953bdd60e1dfcc79797b0c2158e5d861636 Gerrit-Change-Number: 74564 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA
by Karthik Ramasubramanian (Code Review) 19 Apr '23

19 Apr '23

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74334 ) Change subject: soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA ...................................................................... soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA CBFS library performs memory mapped access of the files during loading, verification and de-compression. Even with MTRRs configured correctly, first few file access through memory map are taking longer times to load. Update the SPI DMA driver to load the files into CBFS cache, so that they can be verified and de-compressed with less overhead. This saves ~60 ms in boot time. BUG=None TEST=Build Skyrim BIOS image and boot to OS. Observe ~60 ms improvement with the boot time. Performing additional test to confirm there are no regressions. Before: ======= 970:loading FSP-M 15:starting LZMA decompress (ignore for x86) 760,906 (60,035) 16:finished LZMA decompress (ignore for x86) 798,787 (37,881) 8:starting to load ramstage 17:starting LZ4 decompress (ignore for x86) 1,050,093 (13,790) 18:finished LZ4 decompress (ignore for x86) 1,054,086 (3,993) 971:loading FSP-S 17:starting LZ4 decompress (ignore for x86) 1,067,778 (3,313) 18:finished LZ4 decompress (ignore for x86) 1,068,022 (244) 90:starting to load payload 17:starting LZ4 decompress (ignore for x86) 1,302,155 (11,285) 18:finished LZ4 decompress (ignore for x86) 1,303,938 (1,783) After: ====== 970:loading FSP-M 15:starting LZMA decompress (ignore for x86) 709,542 (12,178) 16:finished LZMA decompress (ignore for x86) 739,379 (29,837) 8:starting to load ramstage 17:starting LZ4 decompress (ignore for x86) 1,001,316 (12,368) 18:finished LZ4 decompress (ignore for x86) 1,001,971 (655) 971:loading FSP-S 17:starting LZ4 decompress (ignore for x86) 1,016,514 (3,031) 18:finished LZ4 decompress (ignore for x86) 1,016,722 (207) 90:starting to load payload 17:starting LZ4 decompress (ignore for x86) 1,244,602 (10,313) 18:finished LZ4 decompress (ignore for x86) 1,244,831 (228) Change-Id: Ie30b6324f9977261c60e55ed509e979ef290f1f1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74334 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp(a)google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/common/block/lpc/spi_dma.c M src/soc/amd/mendocino/Kconfig 2 files changed, 93 insertions(+), 17 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Tim Van Patten: Looks good to me, approved Matt DeVillier: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/lpc/spi_dma.c b/src/soc/amd/common/block/lpc/spi_dma.c index 8fbd9bd..701b61a 100644 --- a/src/soc/amd/common/block/lpc/spi_dma.c +++ b/src/soc/amd/common/block/lpc/spi_dma.c @@ -4,6 +4,7 @@ #include <amdblocks/spi.h> #include <assert.h> #include <boot_device.h> +#include <cbfs.h> #include <commonlib/bsd/helpers.h> #include <commonlib/region.h> #include <console/console.h> @@ -26,22 +27,6 @@ size_t remaining; }; -static void *spi_dma_mmap(const struct region_device *rd, size_t offset, - size_t size __always_unused) -{ - const struct mem_region_device *mdev; - - mdev = container_of(rd, __typeof__(*mdev), rdev); - - return &mdev->base[offset]; -} - -static int spi_dma_munmap(const struct region_device *rd __always_unused, - void *mapping __always_unused) -{ - return 0; -} - static ssize_t spi_dma_readat_mmap(const struct region_device *rd, void *b, size_t offset, size_t size) { @@ -223,6 +208,41 @@ return spi_dma_readat_mmap(rd, b, offset, size); } +static void *spi_dma_mmap(const struct region_device *rd, size_t offset, size_t size) +{ + const struct mem_region_device *mdev; + void *mapping; + + mdev = container_of(rd, __typeof__(*mdev), rdev); + + if (!CONFIG_CBFS_CACHE_SIZE) + return &mdev->base[offset]; + + mapping = mem_pool_alloc(&cbfs_cache, size); + if (!mapping) { + printk(BIOS_INFO, "%s: Could not allocate %zu bytes from memory pool\n", + __func__, size); + /* Fall-back to memory map */ + return &mdev->base[offset]; + } + + if (spi_dma_readat(rd, mapping, offset, size) != size) { + printk(BIOS_ERR, "%s: Error reading into mmap buffer\n", __func__); + mem_pool_free(&cbfs_cache, mapping); + /* Fall-back to memory mapped read - not expected to fail atleast for now */ + spi_dma_readat_mmap(rd, mapping, offset, size); + } + + return mapping; +} + +static int spi_dma_munmap(const struct region_device *rd __always_unused, void *mapping) +{ + if (CONFIG_CBFS_CACHE_SIZE) + mem_pool_free(&cbfs_cache, mapping); + return 0; +} + const struct region_device_ops spi_dma_rdev_ro_ops = { .mmap = spi_dma_mmap, .munmap = spi_dma_munmap, diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index 1abe018..91fd57d 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -243,7 +243,7 @@ config CBFS_CACHE_SIZE hex - default 0x40000 if CBFS_PRELOAD + default 0x40000 if CBFS_PRELOAD || SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA config RO_REGION_ONLY string -- To view, visit https://review.coreboot.org/c/coreboot/+/74334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie30b6324f9977261c60e55ed509e979ef290f1f1 Gerrit-Change-Number: 74334 Gerrit-PatchSet: 7 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/skyrim: Fix eMMC reset GPIO
by Karthik Ramasubramanian (Code Review) 19 Apr '23

19 Apr '23

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74512 ) Change subject: mb/google/skyrim: Fix eMMC reset GPIO ...................................................................... mb/google/skyrim: Fix eMMC reset GPIO On Skyrim variants, the eMMC reset GPIO should be SSD_AUX_RST_L (GPIO6). Update the port_descriptors to link the correct reset GPIO. Data is from the skyrim variant schematics and go/skyrim-gpios. BUG=b:278759559 TEST=reboot: 5 iterations suspend_stress_test: 10 iterations Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I4713b3af23bb7684c9e2e81cf9c8d8a560b41a79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74512 Reviewed-by: Tim Van Patten <timvp(a)google.com> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/skyrim/variants/markarth/port_descriptors.c M src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c 2 files changed, 26 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Tim Van Patten: Looks good to me, but someone else must approve Matt DeVillier: Looks good to me, approved Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c b/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c index 37edb02..330fc46 100644 --- a/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c +++ b/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c @@ -35,7 +35,7 @@ .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, - .gpio_group_id = GPIO_27, + .gpio_group_id = GPIO_6, .clk_req = CLK_REQ1, }, }; diff --git a/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c b/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c index 37edb02..330fc46 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c +++ b/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c @@ -35,7 +35,7 @@ .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, - .gpio_group_id = GPIO_27, + .gpio_group_id = GPIO_6, .clk_req = CLK_REQ1, }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/74512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4713b3af23bb7684c9e2e81cf9c8d8a560b41a79 Gerrit-Change-Number: 74512 Gerrit-PatchSet: 5 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/skyrim: Fix eMMC reset GPIO
by Karthik Ramasubramanian (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Jason Nien, Jon Murphy, Mark Hasemeyer. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74512 ) Change subject: mb/google/skyrim: Fix eMMC reset GPIO ...................................................................... Patch Set 4: Code-Review+2 (1 comment) Patchset: PS4: Submitting this since we have 3 +2s -- To view, visit https://review.coreboot.org/c/coreboot/+/74512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4713b3af23bb7684c9e2e81cf9c8d8a560b41a79 Gerrit-Change-Number: 74512 Gerrit-PatchSet: 4 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Wed, 19 Apr 2023 19:09:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/myst: Enable PCIe devices in devicetree
by Felix Held (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Tim Van Patten. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74112 ) Change subject: mb/google/myst: Enable PCIe devices in devicetree ...................................................................... Patch Set 38: (2 comments) File src/mainboard/google/myst/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/74112/comment/ad096973_7c1789a1 PS38, Line 77: register "gpp_clk_config[0]" = "GPP_CLK_REQ" might be nice to add comments to which device each one is connected to File src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h: https://review.coreboot.org/c/coreboot/+/74112/comment/67bcee84_5f27e683 PS38, Line 11: PCIE_GPP_2_0_DEVFN oh, phoenix' soc/pci_defs.h hasn't been updated yet and is inconsistent with the devicetree names :( i'll push a patch for that one -- To view, visit https://review.coreboot.org/c/coreboot/+/74112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Gerrit-Change-Number: 74112 Gerrit-PatchSet: 38 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Wed, 19 Apr 2023 18:42:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Send CSE EOP Async CMD early
by Tarun Tuli (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Subrata Banik. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74561 ) Change subject: soc/intel/meteorlake: Send CSE EOP Async CMD early ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91ed38edbd5a31d61d4888e1466169a3494d635a Gerrit-Change-Number: 74561 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Wed, 19 Apr 2023 18:33:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Enable asynchronous End-Of-Post
by Tarun Tuli (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Subrata Banik. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74562 ) Change subject: mb/google/rex: Enable asynchronous End-Of-Post ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27b540eeddcada521eba91fcc51504831d6dc855 Gerrit-Change-Number: 74562 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Wed, 19 Apr 2023 18:33:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vendorcode/mediatek/mt8192: Fix set but unused variables
by Arthur Heymans (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Xi Chen, Xixi Chen. Hello Xi Chen, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74543 to look at the new patch set (#5). Change subject: vendorcode/mediatek/mt8192: Fix set but unused variables ...................................................................... vendorcode/mediatek/mt8192: Fix set but unused variables TEST: BUILD_TIMELESS=1 binary remains the same. Change-Id: Ic05a9819764c03184b54c4fc58dbe325fddeae10 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/vendorcode/mediatek/mt8192/dramc/dramc_dvfs.c M src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c M src/vendorcode/mediatek/mt8192/dramc/dramc_top.c M src/vendorcode/mediatek/mt8192/dramc/emi.c M src/vendorcode/mediatek/mt8192/include/dramc_common.h M src/vendorcode/mediatek/mt8192/include/x_hal_io.h 6 files changed, 19 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/74543/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/74543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic05a9819764c03184b54c4fc58dbe325fddeae10 Gerrit-Change-Number: 74543 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: vendorcode/mediatek/mt8192: Fix set but unused variables
by Arthur Heymans (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Xi Chen, Xixi Chen. Hello Xi Chen, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74543 to look at the new patch set (#4). Change subject: vendorcode/mediatek/mt8192: Fix set but unused variables ...................................................................... vendorcode/mediatek/mt8192: Fix set but unused variables TEST: BUILD_TIMELESS=1 binary remains the same. Change-Id: Ic05a9819764c03184b54c4fc58dbe325fddeae10 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/vendorcode/mediatek/mt8192/dramc/dramc_dvfs.c M src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c M src/vendorcode/mediatek/mt8192/dramc/dramc_top.c M src/vendorcode/mediatek/mt8192/dramc/emi.c M src/vendorcode/mediatek/mt8192/include/dramc_common.h M src/vendorcode/mediatek/mt8192/include/x_hal_io.h 6 files changed, 19 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/74543/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic05a9819764c03184b54c4fc58dbe325fddeae10 Gerrit-Change-Number: 74543 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/mediatek/mt8183: Fix set but unused variable
by Arthur Heymans (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Hung-Te Lin, Yidi Lin. Hello Hung-Te Lin, Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74554 to look at the new patch set (#5). Change subject: soc/mediatek/mt8183: Fix set but unused variable ...................................................................... soc/mediatek/mt8183: Fix set but unused variable This fixes a clang warning. Change-Id: I017ed8601e6ec4c66487e9a6f31e93251515e686 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 1 file changed, 13 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/74554/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/74554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I017ed8601e6ec4c66487e9a6f31e93251515e686 Gerrit-Change-Number: 74554 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: newpatchset

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