coreboot-gerrit April 2023

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[S] Change in coreboot[master]: soc/amd/common/block/gfx: Re-add signature check for vbios cache
by Matt DeVillier (Code Review) 19 Apr '23

19 Apr '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74525 ) Change subject: soc/amd/common/block/gfx: Re-add signature check for vbios cache ...................................................................... soc/amd/common/block/gfx: Re-add signature check for vbios cache Commit c7b8809f155a ("soc/amd/common/block/gfx: Use TPM-stored hash for vbios cache validation") replaced checking the vbios signature (first two bytes) with checking against a TPM-stored hash, but there exists an edge case where the empty cache can be hashed and therefore never updated with the correct vbios data. To mitigate this, re-add the signature check to ensure that an empty cache will never be hashed to TPM. BUG=b:255812886 BRANCH=skyrim TEST=build/boot skyrim w/selective GOP enabled, flash full firmware image, ensure GOP driver is run until cache updated with valid data and hashed to TPM. Change-Id: Id06a8cfaa44d346fb2eece53dcf74ee46f4a5352 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/common/block/graphics/graphics.c 1 file changed, 30 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/74525/1 diff --git a/src/soc/amd/common/block/graphics/graphics.c b/src/soc/amd/common/block/graphics/graphics.c index cc52053..9239bd6 100644 --- a/src/soc/amd/common/block/graphics/graphics.c +++ b/src/soc/amd/common/block/graphics/graphics.c @@ -257,11 +257,13 @@ /* * Return true if VBIOS cache data is valid * - * Compare hash of data with hash stored in TPM NVRAM + * Compare first 2 bytes of data with known signature + * and hash of data with hash stored in TPM NVRAM */ bool vbios_cache_is_valid(void) { - return vbios_cache_verify_hash(vbios_data, VBIOS_CACHE_FMAP_SIZE) == CB_SUCCESS; + bool sig_valid = vbios_data[0] == 0x55 && vbios_data[1] == 0xaa; + return sig_valid && vbios_cache_verify_hash(vbios_data, VBIOS_CACHE_FMAP_SIZE) == CB_SUCCESS; } BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, read_vbios_cache_from_fmap, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/74525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id06a8cfaa44d346fb2eece53dcf74ee46f4a5352 Gerrit-Change-Number: 74525 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/skyrim: Fix eMMC reset GPIO
by Jon Murphy (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Jason Nien, Martin Roth, Mark Hasemeyer. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74512 ) Change subject: mb/google/skyrim: Fix eMMC reset GPIO ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74512/comment/bbd184f5_06ae7cc9 PS3, Line 14: None > Can you please confirm that this boots & suspend/resume fine on eMMC SKUs Testing performed by timvp@ on an EVT SKU3 with an 128GB eMMC reboot: 5 iterations suspend_stress_test: 10 iterations -- To view, visit https://review.coreboot.org/c/coreboot/+/74512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4713b3af23bb7684c9e2e81cf9c8d8a560b41a79 Gerrit-Change-Number: 74512 Gerrit-PatchSet: 4 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Wed, 19 Apr 2023 17:20:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/meteoerlake: set power limits dynamically
by Subrata Banik (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Tarun Tuli, Jérémy Compostella, Sumeet R Pawnikar, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74380 ) Change subject: soc/intel/meteoerlake: set power limits dynamically ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > Cf. https://partnerissuetracker.corp.google.com/issues/262499722 comment#16 This is not proper to give `-1` in open source code review by guarding something in access control database. (not all reviewers in coreboot has access to partner database). JFYI if you have some justification to block this patch, please be open here. In summary, we can't rely on Intel FSP default programming while working on coreboot. We always have to find ways to ensure we bring things in open and don't hide behind FSP door. Let me put my concerns here as well The reason, I'm not okay with too much dependency over FSP is that the fact, FSP code and default value can change any time to address the concern from other customers which might create problem for us. Additionally, FSP API mode is never boot tested at FSP side hence, how do someone know the impact of changes certain value on the chromeos devices? -- To view, visit https://review.coreboot.org/c/coreboot/+/74380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20c9bc21dfa79696b07c460dbcedb4fa51838bdb Gerrit-Change-Number: 74380 Gerrit-PatchSet: 4 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 19 Apr 2023 17:13:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: Fix eMMC reset GPIO
by Jon Murphy (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Jason Nien, Jon Murphy, Martin Roth, Mark Hasemeyer. Hello build bot (Jenkins), Jason Nien, Martin Roth, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74512 to look at the new patch set (#4). Change subject: mb/google/skyrim: Fix eMMC reset GPIO ...................................................................... mb/google/skyrim: Fix eMMC reset GPIO On Skyrim variants, the eMMC reset GPIO should be SSD_AUX_RST_L (GPIO6). Update the port_descriptors to link the correct reset GPIO. Data is from the skyrim variant schematics and go/skyrim-gpios. BUG=b:278759559 TEST=reboot: 5 iterations suspend_stress_test: 10 iterations Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I4713b3af23bb7684c9e2e81cf9c8d8a560b41a79 --- M src/mainboard/google/skyrim/variants/markarth/port_descriptors.c M src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c 2 files changed, 20 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/74512/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4713b3af23bb7684c9e2e81cf9c8d8a560b41a79 Gerrit-Change-Number: 74512 Gerrit-PatchSet: 4 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/rex: Enable asynchronous End-Of-Post
by Kapil Porwal (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74562 ) Change subject: mb/google/rex: Enable asynchronous End-Of-Post ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27b540eeddcada521eba91fcc51504831d6dc855 Gerrit-Change-Number: 74562 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Wed, 19 Apr 2023 16:52:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Send CSE EOP Async CMD early
by Kapil Porwal (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74561 ) Change subject: soc/intel/meteorlake: Send CSE EOP Async CMD early ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91ed38edbd5a31d61d4888e1466169a3494d635a Gerrit-Change-Number: 74561 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Wed, 19 Apr 2023 16:52:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: [WIP] ACPI: Add usb_charge_mode_from_gnvs()
by Kyösti Mälkki (Code Review) 19 Apr '23

19 Apr '23

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74524 ) Change subject: [WIP] ACPI: Add usb_charge_mode_from_gnvs() ...................................................................... [WIP] ACPI: Add usb_charge_mode_from_gnvs() Used together with (old API?) of ChromeEC to control USB port power for S3/S4/S5 sleep states. Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/acpi_pm.c M src/ec/google/chromeec/smihandler.c M src/ec/google/chromeec/smm.h M src/include/acpi/acpi_gnvs.h M src/mainboard/google/auron/smihandler.c M src/mainboard/google/butterfly/smihandler.c M src/mainboard/google/cyan/smihandler.c M src/mainboard/google/link/smihandler.c M src/mainboard/google/parrot/smihandler.c M src/mainboard/google/rambi/smihandler.c M src/mainboard/google/slippy/smihandler.c M src/mainboard/google/stout/smihandler.c M src/mainboard/intel/strago/smihandler.c 13 files changed, 104 insertions(+), 99 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/74524/1 diff --git a/src/acpi/acpi_pm.c b/src/acpi/acpi_pm.c index 40a3fbd..6786f44 100644 --- a/src/acpi/acpi_pm.c +++ b/src/acpi/acpi_pm.c @@ -59,3 +59,29 @@ } return 0; } + +#if CONFIG(ACPI_SOC_NVS) && ENV_SMM + +#include <acpi/acpi_gnvs.h> +#include <cpu/x86/smm.h> +#include <soc/nvs.h> + +void usb_charge_mode_from_gnvs(uint8_t slp_typ, bool *usb0_disable, bool *usb1_disable) +{ + if (!gnvs) + return; + + switch (slp_typ) { + case ACPI_S3: + *usb0_disable = (gnvs->s3u0 == 0); + *usb1_disable = (gnvs->s3u1 == 0); + break; + case ACPI_S4: /* from slippy */ + case ACPI_S5: + *usb0_disable = (gnvs->s5u0 == 0); + *usb1_disable = (gnvs->s5u1 == 0); + break; + } +} + +#endif diff --git a/src/ec/google/chromeec/smihandler.c b/src/ec/google/chromeec/smihandler.c index cd0cd4f..599a66e 100644 --- a/src/ec/google/chromeec/smihandler.c +++ b/src/ec/google/chromeec/smihandler.c @@ -45,6 +45,15 @@ ; } +void chromeec_set_usb_charge_mode(bool u0disable, bool u1disable) +{ + if (u0disable) + google_chromeec_set_usb_charge_mode(0, USB_CHARGE_MODE_DISABLED); + + if (u1disable) + google_chromeec_set_usb_charge_mode(1, USB_CHARGE_MODE_DISABLED); +} + void chromeec_smi_sleep(int slp_type, uint64_t s3_mask, uint64_t s5_mask) { if (!google_chromeec_is_uhepi_supported()) { diff --git a/src/ec/google/chromeec/smm.h b/src/ec/google/chromeec/smm.h index 6f209a7..5baf213 100644 --- a/src/ec/google/chromeec/smm.h +++ b/src/ec/google/chromeec/smm.h @@ -8,6 +8,8 @@ /* Process all events from the EC when EC triggered an SMI#. */ void chromeec_smi_process_events(void); +void chromeec_set_usb_charge_mode(bool u0disable, bool u1disable); + /* * Set wake masks according to sleep type, clear SCI and SMI masks, * and clear any pending events. diff --git a/src/include/acpi/acpi_gnvs.h b/src/include/acpi/acpi_gnvs.h index ef6ec29..fe6924f 100644 --- a/src/include/acpi/acpi_gnvs.h +++ b/src/include/acpi/acpi_gnvs.h @@ -18,6 +18,9 @@ static inline int acpi_reset_gnvs_for_wake(struct global_nvs **gnvs) { return -1; } #endif +/* Return GNVS fields for USB0/1 disablement for S3/S4/S5 sleep states. */ +void usb_charge_mode_from_gnvs(uint8_t slp_typ, bool *usb0_disable, bool *usb1_disable); + /* * These functions populate the gnvs structure in acpi table. * Defined as weak in common acpi as gnvs structure definition is diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index 237a2b3..bba9fc23 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <soc/pm.h> @@ -8,7 +9,6 @@ #include <ec/google/chromeec/smm.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> #include <soc/iomap.h> -#include <soc/nvs.h> #include "ec.h" #include <variant/onboard.h> @@ -35,29 +35,21 @@ void mainboard_smi_sleep(u8 slp_typ) { + bool u0disable = 0, u1disable = 0; + /* Disable USB charging if required */ + /* NOTE: s3u0 and s5u0 for usb0 also control usb1 here.*/ + usb_charge_mode_from_gnvs(slp_typ, &u0disable, &u1disable); + chromeec_set_usb_charge_mode(u0disable, u0disable); + switch (slp_typ) { case ACPI_S3: - if (gnvs->s3u0 == 0) { - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - } - mainboard_disable_gpios(); /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); break; case ACPI_S5: - if (gnvs->s5u0 == 0) { - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - } - mainboard_disable_gpios(); /* Enable wake events */ diff --git a/src/mainboard/google/butterfly/smihandler.c b/src/mainboard/google/butterfly/smihandler.c index 23bd683..b72b7da 100644 --- a/src/mainboard/google/butterfly/smihandler.c +++ b/src/mainboard/google/butterfly/smihandler.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <soc/nvs.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/me.h> #include <northbridge/intel/sandybridge/sandybridge.h> @@ -13,8 +13,11 @@ void mainboard_smi_sleep(u8 slp_typ) { + bool u0disable = 0, u1disable = 0; + /* Tell the EC to Enable USB power for S3 if requested */ - if (gnvs->s3u0 != 0 || gnvs->s3u1 != 0) + usb_charge_mode_from_gnvs(3, &u0disable, &u1disable); + if (!u0disable || !u1disable) ec_mem_write(EC_EC_PSW, ec_mem_read(EC_EC_PSW) | EC_PSW_USB); /* Disable wake on USB, LAN & RTC */ diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 8f06cf4..562a6bd 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -1,13 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <device/mmio.h> #include <console/console.h> #include <cpu/x86/smm.h> #include "ec.h" #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> -#include <soc/nvs.h> #include <soc/pm.h> #include <soc/gpio.h> @@ -30,32 +30,22 @@ void mainboard_smi_sleep(uint8_t slp_typ) { + bool u0disable = 0, u1disable = 0; void *addr; uint32_t mask; /* Disable USB charging if required */ + usb_charge_mode_from_gnvs(slp_typ, &u0disable, &u1disable); + chromeec_set_usb_charge_mode(u0disable, u1disable); + switch (slp_typ) { case ACPI_S3: - if (gnvs->s3u0 == 0) - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - if (gnvs->s3u1 == 0) - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); /* Enable wake pin in GPE block. */ enable_gpe(WAKE_GPIO_EN); break; case ACPI_S5: - if (gnvs->s5u0 == 0) - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - if (gnvs->s5u1 == 0) - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); diff --git a/src/mainboard/google/link/smihandler.c b/src/mainboard/google/link/smihandler.c index 4a9dfb0..17ef23a 100644 --- a/src/mainboard/google/link/smihandler.c +++ b/src/mainboard/google/link/smihandler.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <soc/nvs.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/me.h> #include <northbridge/intel/sandybridge/sandybridge.h> @@ -21,25 +21,11 @@ void mainboard_smi_sleep(u8 slp_typ) { + bool u0disable = 0, u1disable = 0; + /* Disable USB charging if required */ - switch (slp_typ) { - case ACPI_S3: - if (gnvs->s3u0 == 0) - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - if (gnvs->s3u1 == 0) - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - break; - case ACPI_S5: - if (gnvs->s5u0 == 0) - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - if (gnvs->s5u1 == 0) - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - break; - } + usb_charge_mode_from_gnvs(slp_typ, &u0disable, &u1disable); + chromeec_set_usb_charge_mode(u0disable, u1disable); /* Disable SCI and SMI events */ google_chromeec_set_smi_mask(0); diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index 7d519e3..08be5b0 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <halt.h> -#include <soc/nvs.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/pmutil.h> @@ -48,6 +48,8 @@ void mainboard_smi_sleep(u8 slp_typ) { + bool u0disable = 0, u1disable = 0; + /* Disable SCI and SMI events */ /* Clear pending events that may trigger immediate wake */ @@ -55,7 +57,8 @@ /* Enable wake events */ /* Tell the EC to Disable USB power */ - if (gnvs->s3u0 == 0 && gnvs->s3u1 == 0) { + usb_charge_mode_from_gnvs(3, &u0disable, &u1disable); + if (u0disable && u1disable) { ec_kbc_write_cmd(0x45); ec_kbc_write_ib(0xF2); } diff --git a/src/mainboard/google/rambi/smihandler.c b/src/mainboard/google/rambi/smihandler.c index 3eb1d1d..affa3b0 100644 --- a/src/mainboard/google/rambi/smihandler.c +++ b/src/mainboard/google/rambi/smihandler.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <console/console.h> #include <cpu/x86/smm.h> @@ -8,7 +9,6 @@ #include <ec/google/chromeec/smm.h> #include "ec.h" -#include <soc/nvs.h> #include <soc/pm.h> /* The wake gpio is SUS_GPIO[0]. */ @@ -24,29 +24,20 @@ void mainboard_smi_sleep(uint8_t slp_typ) { + bool u0disable = 0, u1disable = 0; + /* Disable USB charging if required */ + usb_charge_mode_from_gnvs(slp_typ, &u0disable, &u1disable); + chromeec_set_usb_charge_mode(u0disable, u1disable); + switch (slp_typ) { case ACPI_S3: - if (gnvs->s3u0 == 0) - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - if (gnvs->s3u1 == 0) - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); /* Enable wake pin in GPE block. */ enable_gpe(WAKE_GPIO_EN); break; case ACPI_S5: - if (gnvs->s5u0 == 0) - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - if (gnvs->s5u1 == 0) - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); break; diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index 71e97af..3ac2152 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <soc/nvs.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/lynxpoint/me.h> @@ -30,16 +30,14 @@ void mainboard_smi_sleep(u8 slp_typ) { + bool u0disable = 0, u1disable = 0; + /* Disable USB charging if required */ + usb_charge_mode_from_gnvs(slp_typ, &u0disable, &u1disable); + chromeec_set_usb_charge_mode(u0disable, u1disable); + switch (slp_typ) { case ACPI_S3: - if (gnvs->s3u0 == 0) - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - if (gnvs->s3u1 == 0) - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - /* Prevent leak from standby rail to WLAN rail in S3. */ set_gpio(GPIO_WLAN_DISABLE_L, 0); set_gpio(GPIO_PP3300_CODEC_EN, 0); @@ -51,13 +49,6 @@ break; case ACPI_S4: case ACPI_S5: - if (gnvs->s5u0 == 0) - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - if (gnvs->s5u1 == 0) - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - /* Prevent leak from standby rail to WLAN rail in S5. */ set_gpio(GPIO_WLAN_DISABLE_L, 0); set_gpio(GPIO_PP3300_CODEC_EN, 0); diff --git a/src/mainboard/google/stout/smihandler.c b/src/mainboard/google/stout/smihandler.c index 30637ab..578bdb5 100644 --- a/src/mainboard/google/stout/smihandler.c +++ b/src/mainboard/google/stout/smihandler.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <device/pci_ops.h> #include <console/console.h> #include <cpu/x86/smm.h> @@ -38,6 +39,8 @@ void mainboard_smi_sleep(u8 slp_typ) { + bool u0disable = 0, u1disable = 0; + /* * Tell the EC to Enable USB power for S3 if requested. * Bit0 of 0x0D/Bit0 of 0x26 @@ -47,7 +50,9 @@ * charge smart phone. * 1/1 USB on, yellow port in AUTO mode and didn't support wake up system. */ - if (gnvs->s3u0 != 0 || gnvs->s3u1 != 0) { + usb_charge_mode_from_gnvs(3, &u0disable, &u1disable); + + if (!u0disable || !u1disable) { ec_write(EC_PERIPH_CNTL_3, ec_read(EC_PERIPH_CNTL_3) | 0x00); ec_write(EC_USB_S3_EN, ec_read(EC_USB_S3_EN) | 0x01); printk(BIOS_DEBUG, "USB wake from S3 enabled.\n"); diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c index a625b62..3daf3b6 100644 --- a/src/mainboard/intel/strago/smihandler.c +++ b/src/mainboard/intel/strago/smihandler.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <console/console.h> #include <cpu/x86/smm.h> #include "ec.h" @@ -8,7 +9,6 @@ #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> -#include <soc/nvs.h> #include <soc/pm.h> #include <soc/gpio.h> @@ -29,29 +29,20 @@ void mainboard_smi_sleep(uint8_t slp_typ) { + bool u0disable = 0, u1disable = 0; + /* Disable USB charging if required */ + usb_charge_mode_from_gnvs(slp_typ, &u0disable, &u1disable); + chromeec_set_usb_charge_mode(u0disable, u1disable); + switch (slp_typ) { case ACPI_S3: - if (gnvs->s3u0 == 0) - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - if (gnvs->s3u1 == 0) - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); /* Enable wake pin in GPE block. */ enable_gpe(WAKE_GPIO_EN); break; case ACPI_S5: - if (gnvs->s5u0 == 0) - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - if (gnvs->s5u1 == 0) - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); break; -- To view, visit https://review.coreboot.org/c/coreboot/+/74524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9 Gerrit-Change-Number: 74524 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/meteoerlake: set power limits dynamically
by Jérémy Compostella (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Tarun Tuli, Sumeet R Pawnikar, Eric Lai. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74380 ) Change subject: soc/intel/meteoerlake: set power limits dynamically ...................................................................... Patch Set 4: Code-Review-1 (1 comment) Patchset: PS4: Cf. https://partnerissuetracker.corp.google.com/issues/262499722 comment#16 -- To view, visit https://review.coreboot.org/c/coreboot/+/74380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20c9bc21dfa79696b07c460dbcedb4fa51838bdb Gerrit-Change-Number: 74380 Gerrit-PatchSet: 4 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 19 Apr 2023 16:18:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/amd/birman: Enable PCIe RTD3 support
by Felix Held (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Jason Glenesk, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74247 ) Change subject: mb/amd/birman: Enable PCIe RTD3 support ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5eac65125c11dd04c5dbb5996c947ad734acdae3 Gerrit-Change-Number: 74247 Gerrit-PatchSet: 7 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 19 Apr 2023 15:35:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/amd/birman: Update DXIO descriptors per schematic
by Felix Held (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Jason Glenesk, Paul Menzel, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69705 ) Change subject: mb/amd/birman: Update DXIO descriptors per schematic ...................................................................... Patch Set 18: Code-Review+2 (1 comment) File src/mainboard/amd/birman/port_descriptors_phoenix.c: https://review.coreboot.org/c/coreboot/+/69705/comment/f76401d3_bb185349 PS16, Line 113: .start_logical_lane = 15, \ : .end_logical_lane = CONFIG(WLAN01) ? 14 : 15, \ > Tested and checked the logs in FSP - it detects the reversed order case and handles it properly thanks for testing. wasn't sure if the dxio programming will like this or not -- To view, visit https://review.coreboot.org/c/coreboot/+/69705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76cf6715b60a1857bf58349d70a623bf043594fe Gerrit-Change-Number: 69705 Gerrit-PatchSet: 18 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 19 Apr 2023 15:34:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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